Doherty amplifier system

A Doherty amplifier system comprising:

• a carrier amplifier having a carrier drain bias input, a main input for receiving a first portion of a radio frequency (RF) signal, and a main output in communication with a RF signal output;
• a peak amplifier having a peak drain bias input, a peak gate bias input, a peak input for receiving a second portion of the RF signal, and a peak output in communication with the RF signal output;
• a programmable bias controller comprising:
• a controller interface configured to receive peak-to-average power ratio (PAPR) data associated with a basestation;
• and
• a processor coupled to the controller interface and a memory with a bias look-up table, wherein the processor is configured, in response to the PAPR data, to determine bias levels by way of the look-up table;
• and
• a carrier drain bias generator coupled between the processor and the carrier drain bias input, wherein the carrier drain bias generator comprises a second digital-to-analog converter having a second digital input coupled to the processor and a second analog output in communication with the carrier drain bias input and is configured to output a carrier drain bias level determined by the processor;
• a peak drain bias generator coupled between the processor and the peak drain bias input, wherein the peak drain bias generator comprises a third digital-to-analog converter having a third digital input coupled to the processor and a third analog output in communication with the peak drain bias input and is configured to output a peak drain bias level determined by the processor;
• and
• a peak gate bias generator coupled between the processor and the gate bias input, wherein the peak bias generator comprises a first digital-to-analog converter having a first digital input coupled to the processor and a first analog output in communication with the peak gate bias input and is configured to output a peak gate bias level determined by the processor;
• a saturation detector coupled to the main output;
• and
• an analog-to-digital converter coupled between the saturation detector and the processor, wherein the analog-to-digital converter is configured to receive an analog output from the saturation detector and send a digital saturation value to the processor, wherein the processor is further configured to respond to the digital saturation value and apply the bias levels to the carrier drain bias input, the peak drain bias input, and the peak gate bias input to maintain an amplifier efficiency between 30% and 78.5%.