Handling of errors in generation of phase control signals by a phase controller of a multi- phase switching converter

A method of handling errors in generation of phase control signals, said method performed in a phase controller of a multi-phase switching converter, said multi-phase switching converter to provide a regulated supply voltage from an input voltage, said phase controller to provide corresponding phase control signals to a plurality of power stages, each power stage operable to connect said input voltage to a corresponding inductor when a corresponding phase control signal of a plurality of control signals changes to a first state such that said plurality of power stages together operate to provide said regulated supply voltage, said method comprising:

• generating a common control signal having a transition type to indicate time instances of assertions of a plurality of timing signals;
• generating a respective timing signal in said plurality of timing signals for each power stage of said plurality of power stages, wherein said corresponding phase control signal changes to said first state timed according to an assertion of said respective timing signal;
• detecting a first error condition comprising assertion of more than one of said plurality of timing signals in response to an instance of said transition type of said common control signal;
• and
• performing a first corrective action to avoid said first error condition in a first future duration following said detection of said first error condition.

A phase distributor of a phase controller of a multi-phase switching converter, said phase controller to provide corresponding phase control signals to a plurality of power stages of said multi-phase switching converter, each power stage designed to connect a power source to a corresponding inductor when a corresponding phase control signal is asserted such that said plurality of power stages together operate to provide a regulated supply voltage, said phase distributor comprising:

• a plurality of ring cells connected in a circular sequence, wherein each ring cell corresponds to a respective power stage of said plurality of power stages and comprises a flip-flop clocked by a common control signal generated by a control block of said phase controller, wherein during normal operation the Q-outputs of the respective flip-flops are sequentially asserted in a round-robin fashion to thereby trigger a start of a corresponding phase control signal of said plurality of phase control signals, the Q-output of the flip-flop of only one ring cell being asserted in any one cycle of said common control signal during said normal operation;
• a plurality of correction cells, wherein each correction cell in said plurality of correction cells corresponds to a respective ring cell in said plurality of rings cells and receives a first set of signals from said respective ring cell, each correction cell to provide a corresponding correction signal to said respective ring cell upon occurrence of one or more error conditions in said plurality of ring cells;
• and
• a detector block coupled to receive a second set of signals from said plurality of correction cells, said detector block to detect said one or more error conditions based on said second set of signals, and upon detection of an error condition to generate an output signal coupled to each of said plurality of ring cells, said output signal to cause each of said corresponding correction signals to perform a portion of a corrective action in said respective ring cell.