Device and methods for digital switched capacitor DC-DC converters with reduced analog circuitry
AssigneeMicrochip Technology Incorporated
InventorsAjay Kumar, Paul Walker, Ibiyemi Omole, Daniel Meacham, Arvind Madan, Santosh Patel
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Abstract
A switched-capacitor DC-DC converter circuit may convert an input voltage into a desired output voltage level. A comparator may compare a desired voltage level to a divided version of the output voltage. A fully digital control circuit comprising a frequency divider circuit, a counter circuit, a digital control logic circuit and a gain selection circuit may generate a gain value, and a phase generator may convert the gain value into clock phase signals and control settings to control a switch array to select capacitors to produce a desired output voltage.
Claims20
A DC-DC converter device comprising:
- a switch array circuit to receive an input voltage, a plurality of clock phase signals and a plurality of control settings, the switch array circuit comprising a plurality of switches coupled to a plurality of capacitors;
- a voltage divider coupled to the output of the switch array circuit;
- a first comparator with a non-inverting input coupled to the output of the voltage divider, and an inverting input coupled to a reference voltage;
- a frequency divider circuit with a first input coupled to the output of the first comparator and a second input coupled to an oscillator;
- a counter circuit with an input coupled to the output of the frequency divider circuit, the counter circuit to integrate the output of the frequency divider circuit;
- a digital control logic circuit coupled to the output of the counter circuit;
- a gain selection circuit coupled to the output of the digital control logic circuit, the gain selection circuit to output a gain setting based on the output of the digital control logic circuit and based on the plurality of capacitors;
- a second comparator with an inverting input coupled to a target voltage and non-inverting input coupled to the output voltage, the output of the second comparator coupled to the memory circuit, and
- a phase generator circuit to generate the plurality of clock phase signals and control settings based on the output of an AND gate and the output of the gain selection circuit, the AND gate comprising a first input coupled to the oscillator and a second input coupled to the output of the comparator, wherein
- the phase generator circuit comprising a set-reset memory circuit coupled to a non-overlapping clock generator.
A method comprising:
- driving a comparator with a desired output voltage and a divided version of an output voltage;
- dividing the output of the comparator with an oscillator signal to generate a divider output;
- integrating the divider output with a counter circuit to generate a counter output;
- converting the counter circuit output to a gain setting;
- generating clock phase signals and control settings based on the gain setting, an oscillator signal and the output of the comparator, the clock phase signals to be generated by a phase generator circuit comprising a set-reset memory circuit coupled to a non-overlapping clock generator;
- and
- driving a switch array circuit with the clock phase signals and control settings to generate the output voltage,
- the method further comprising a second comparator with an inverting input coupled to a target voltage and non-inverting input coupled to the output voltage, the output of the second comparator coupled to the memory circuit.
Dependencies are inferred from the claim text.