Scalable multi beamforming topology supporting an electronically steered array antenna

An electronically steered digital beamforming antenna array system comprising:

• a plurality of pairs of branches, each branch comprising a respective chain of a plurality of digital beamforming (DBF) integrated circuits (ICs) connected in series via a bus, the bus comprising a Serializer/Deserializer (SerDes), wherein the plurality of branches comprises at least two DBF chains that operate in parallel and in a synchronized manner to reduce latency relative to a single daisy-chain of DBF ICs;
• one or more splitter/combiner (S/C) ICs connecting together each of the branches of said pairs;
• and
• one or more layers of further splitter/combiner (S/C) ICs arranged in a hierarchical tree, wherein each of the further S/C ICs connects exactlytwo S/C ICs on one end and connects, on the other end, to (i) the modem or (ii) a further S/C IC of a different layer, such that signal combining and splitting is performed across the layers to provide deterministic latency as the number of antenna elements increases,
• wherein each of said DBF ICs comprises phase shifting circuitries, delay circuitries, memory circuitries, and bus controlling circuitries,
• wherein, in a receiver configuration, coherent combining is performed by dividing the antenna array into the parallel synchronized DBF chains and combining outputs of the DBF chains via the hierarchical tree of S/C ICs such that a signal propagation from the DBF IC to the modem depends on a depth of the hierarchical tree;
• wherein each of the S/C ICs comprise a splitter and a combiner,
• wherein a number of the one or more layers of further S/C ICs is selected in order to support a scalable topology of an increased number of antenna elements, and
• wherein the hierarchical tree of S/C ICs is selected such that memory required in each DBF IC for signal delaying to enable coherent combining is reduced relative to a single-chain topology as the number of antenna elements increases.