Memory device including error logging device and operating methods thereof

An error logging device, comprising:

• a fault detection circuit configured to output a fault address with a fault input signal;
• an address storage circuit configured to store the fault address as a start fault address according to a reset signal and the fault input signal, store the fault address as a first comparison address according to the fault input signal inputted with an odd-numbered order, and store the fault address as a second comparison address according to the fault input signal inputted with an even-numbered order;
• a finite state machine (FSM) configured to update fault mode information according to a result of comparing the first comparison address and the second comparison address;
• and
• an error information output circuit configured to output error information including the fault mode information and the start fault address according to an error information request command.

An error logging method, comprising:

• initializing fault mode information according to a reset signal;
• storing a fault address as a starting fault address according to a fault input signal input for a first time after initializing, and updating the fault mode information;
• storing the fault address as a first comparison address according to the fault input signal input with an odd-numbered order, storing the fault address as a second comparison address according to the fault input signal input with an even-numbered order, and updating the fault mode information according to a result of comparing the first comparison address and the second comparison address;
• and
• outputting error information including the fault mode information and the start fault address according to an error information request command.

A memory system, comprising:

• a memory controller;
• and
• a memory device configured to perform a scrub operation on each of a plurality of rows under a control of the memory controller and generate a reset signal according to the scrub operation,
• wherein the memory controller includes:
• a fault detection circuit configured to generate a fault address according to the scrub operation for each of the plurality of rows and sequentially output the fault addresses together with a fault input signal;
• and
• a fault information management circuit configured to generate first to third fault addresses using the fault addresses, to store the first fault address as a start fault address, to store the second and third fault addresses, and to generate fault mode information that defines a relationship between the start fault address and the second and third fault addresses, according to the fault input signal and the reset signal, and to output error information including the start fault address and the fault mode information.