Storage array

A storage array, comprising memory cells arranged in a matrix array, each memory cell comprising two memories, one P-channel field effect transistor, a first N-channel field effect transistor and a second N-channel field effect transistors alternately connected to the P-channel field effect transistor;

• wherein
• a source of the P-channel field effect transistor is connected to a drain of the first N-channel field effect transistor,
• a drain of the P-channel field effect transistor is connected to a source of the second N-channel field effect transistor, and
• the two memories are respectively configured to be connected to the source of the P-channel field effect transistor and the source of the second N-channel field effect transistor;
• wherein the first N-channel field effect transistor, the P-channel field effect transistor, and the second N-channel field effect transistor are connected in sequence;
• wherein
• gates of the first N-channel field-effect transistor, the second N-channel field-effect transistor, and the P-channel field-effect transistor are connected to different word lines respectively, and
• a source of the first N-channel field-effect transistor and a source of the second N-channel field-effect transistor are connected to different source lines respectively;
• wherein the storage array comprises M x N memory cells, wherein M represents the number of rows, N represents the number of columns, the word lines comprise a word line N connected to gates of the N-channel field effect transistors and a word line P connected to a gate of the P-channel field effect transistor,
• wherein the memory cells in the same row are configured to share the word line N and a bit line, and memory cells in the same column are configured to share the word line P and a source line.