Nonvolatile memory with self-tracking IREF

A nonvolatile memory, comprising:

• a plurality of memory cells organized into M wordlines and N array bitlines;
• a plurality of differential reference cells, each differential reference cell of the plurality of differential reference cells is addressable by a different one of the M wordlines of the plurality of memory cells, wherein each differential reference cell comprises a first reference memory cell and a second reference memory cell, each first reference memory cell electrically connected to a first reference bitline and each second reference memory cell electrically connected to a second reference bitline;
• a plurality of differential sense amplifiers each configured to receive an electrical signal corresponding to a corresponding one of the array bitlines;
• and
• a reference current generator coupled to the first and second reference bitlines, the reference current generator configured to direct a reference current to the differential sense amplifiers.

A method of fabricating an IC device including a nonvolatile memory, the method comprising:

• forming a memory array over a semiconductor substrate, the memory array including a plurality of bitcells addressable by wordlines and array bitlines;
• forming a plurality of differential reference cells over the semiconductor substrate, each differential reference cell of the plurality of differential reference cells electrically connected to a different one of the wordlines of the memory array, a differential reference cell of the plurality of differential reference cells comprising a first reference memory cell and a second reference memory cell, the first reference memory cell operable to produce a first current and the second reference memory cell operable to produce a second current;
• forming a reference current generator over the semiconductor substrate, the reference current generator configured to receive the first and second currents via respective first and second current paths and to output a reference current that is a fraction less than unity of a sum of the first current and the second current;
• and
• forming a differential sense amplifier over the semiconductor substrate, the differential sense amplifier configured to receive the reference current and a bit current corresponding to a selected one of the plurality of bitcells, and to
• output a read bit value corresponding to the selected one of the plurality of bitcells in response to the reference current and the bit current.