Memory device with in-memory searching (IMS) cells and method of Euclidean distance IMS cell encoding

A memory device, comprising:

• a first memory string comprising a first switch element and configured to generate a first cell current signal;
• and
• a second memory string comprising a second switch element and configured to generate a second cell current signal,
• wherein the first switch element and the second switch element are configured to operate as a first memory cell storing a first store bit,
• a control terminal of the first switch element and a control terminal of the second switch element are configured to receive a first word line signal and a second word line signal, respectively,
• the first word line signal and the second word line signal are configured to carry a first input bit, and
• a summation of a current value of the first cell current signal and a current value of the second cell current signal is proportional to a square of a difference between a logic value of the first store bit and a logic value of the first input bit,
• wherein when the first store bit has a first logic value, the first switch element has a first threshold voltage level,
• when the first store bit has a second logic value, the first switch element has a second threshold voltage level,
• when the first input bit has the first logic value, the first word line signal has a first voltage level,
• when the first input bit has the second logic value, the first word line signal has a second voltage level, and
• a difference between the first threshold voltage level and the second threshold voltage level is equal to a difference between the first voltage level and the second voltage level,
• wherein when the first store bit has the first logic value, the first switch element has a third threshold voltage level,
• when the first store bit has the second logic value, the first switch element has a fourth threshold voltage level,
• when the first input bit has the first logic value, the first word line signal has a third voltage level,
• when the first input bit has the second logic value, the first word line signal has a fourth voltage level, and
• a difference between the third threshold voltage level and the fourth threshold voltage level is equal to a difference between the third voltage level and the fourth voltage level.