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US 12,755,788 B2Granted
Address fault detection in a memory system
AssigneeSilicon Storage Technology, Inc.
InventorHieu Van Tran
Life of this patent
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Abstract
Various examples of memory systems comprising an address fault detection system are disclosed. The memory system comprises a first memory array, a row decoder, and an address fault detection system comprising a second array, wherein the row decoder decodes row addresses into word lines, each word line coupled to a row of cells in the first array and a row of cells in the second array. The second array contains digital bits and/or analog values that are used to identify address faults.
Claims16
A memory system, comprising:
- a memory array comprising a first set of memory cells arranged in rows and columns;
- a row decoder configured to receive one of M row addresses as an input, the row decoder coupled to a plurality of word lines, wherein each of the M row addresses corresponds to a word line in the plurality of word lines and wherein each word line is coupled to a row of cells in the first set of memory cells;
- and
- an address fault detection array comprising a second set of memory cells arranged in rows and columns, wherein each of the plurality of word lines is coupled to a row of cells in the second set of memory cells containing an N-bit encoded word such that each of the M row addresses corresponds to an N-bit encoded word where N is an integer and each N-bit encoded word comprises:
- one or more K-bit groups;
- and
- one or more L-bit groups;
- wherein each of the K-bit and L-bit groups contain only one “1” bit, K and L are integers, K≤N, L≤N, K>2, L>2, and the sum of the number of bits in the one or more K-bit groups and the one or more L-bit groups is N, and wherein the same K-bit groups and L-bit groups are applied to each of the N-bit encoded words.
5 more elements
Dependencies are inferred from the claim text.