Low-power programmable erasable nonvolatile memory

A low-power programmable erasable nonvolatile memory comprising:

• a plurality of common-source lines arranged in parallel;
• a plurality of word lines arranged in parallel, wherein the plurality of word lines are parallel to the plurality of common-source lines;
• a plurality of bit lines arranged in parallel, wherein the plurality of bit lines are perpendicular to the plurality of common-source lines;
• a plurality of memory arrays each coupled to one of the plurality of common-source lines, one of the plurality of word lines, and four of the plurality of bit lines;
• a first electronic switch and a second electronic switch;
• a decoding device coupled to the plurality of common-source lines, the plurality of word lines, the plurality of bit lines, a high voltage, a middle voltage, a low voltage, and a grounding voltage, wherein the high voltage is greater than the middle voltage, the middle voltage is greater than the low voltage, and the low voltage is greater than the grounding voltage;
• at least one first storage capacitor with one end thereof coupled to a reference voltage, and another end of the at least one first storage capacitor is coupled to the decoding device through the first electronic switch;
• at least one second storage capacitor with one end thereof coupled to a supply voltage, and another end of the at least one second storage capacitor is coupled to the decoding device through the second electronic switch;
• and
• a voltage boosting circuit coupled to the at least one first storage capacitor, wherein when the first electronic switch and the second electronic switch are turned off, the voltage boosting circuit receives an input voltage to charge the at least one first storage capacitor to have a charging voltage greater than the reference voltage;
• wherein when the first electronic switch and the second electronic switch are turned on, the decoding device biases one of the plurality of memory arrays as a target memory array based on voltages coupled to the decoding device, and the at least one first storage capacitor charges the at least one second storage capacitor through the target memory array to perform a programming activity or an erasing activity.