US 12,755,786 B2Granted

Method and apparatus for initializing resistive random access memory and electronic device

AssigneeXiamen Industrial Technology Research Institute Co., Ltd.

InventorsAnqiao Chen, Tingying Shen, Taiwei Chiu, Szu-Chun Kang, Wuxin Li, Jinmao Yan, Enping Cheng

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Abstract

A method and apparatus for initializing an RRAM and an electronic device are provided. The method includes: inputting a plurality of pulses of a first voltage into an RRAM until memory cells in the RRAM transition from a high resistance state to a low resistance state; inputting a plurality of pulses of a second voltage, a third voltage . . . and an Nth voltage into the RRAM, so that resistance values of the memory cells reach a corresponding preset value, respectively. Voltage values of the first voltage to the Nth voltage gradually decrease. When a total number of input pulses of an ith voltage is greater than a second preset threshold and a resistance change rate is less than a rate threshold, a plurality of pulses of an increased ith voltage are input into the RRAM until the resistance values of the memory cells reach an ith preset value.

Claims10

Dependent claims

A method for initializing a resistive random access memory, comprising:

inputting a plurality of pulses of a first voltage into the resistive random access memory until memory cells in the resistive random access memory transition from a high resistance state to a low resistance state;
inputting a plurality of pulses of a second voltage into the resistive random access memory until resistance values of the memory cells in the resistive random access memory reach a second preset value;
wherein the second preset value is less than the resistance values of the memory cells when transitioning from the high resistance state to the low resistance state;
inputting a plurality of pulses of a third voltage into the resistive random access memory until the resistance values of the memory cells in the resistive random access memory reach a third preset value;
wherein the third preset value is less than the second preset value;
and so on, inputting a plurality of pulses of an Nth voltage into the resistive random access memory until the resistance values of the memory cells in the resistive random access memory reach an Nth preset value;
wherein N is greater than or equal to 3, voltage values of the first voltage, the second voltage, the third voltage . . . and the Nth voltage gradually decrease, the Nth preset value is less than an (N−1)th preset value, and the Nth preset value is a target resistance value achieved to complete an initialization of the memory cells;
wherein inputting a plurality of pulses of an ith voltage into the resistive random access memory until the resistance values of the memory cells in the resistive random access memory reach an ith preset value comprises:
inputting the plurality of pulses of the ith voltage into the resistive random access memory;
when a total number of the input pulses of the ith voltage is greater than a second preset threshold and a resistance change rate is less than a rate threshold, increasing the ith voltage to obtain an increased ith voltage, and inputting a plurality of pulses of the increased ith voltage into the resistive random access memory until the resistance values of the memory cells in the resistive random access memory reach the ith preset value;
wherein i represents any of two, three . . . N−1, and N.

8 more elements

An apparatus for initializing a resistive random access memory, comprising:

a first input unit, configured to input a plurality of pulses of a first voltage into the resistive random access memory until memory cells in the resistive random access memory transition from a high resistance state to a low resistance state;
a second input unit, configured to input a plurality of pulses of a second voltage into the resistive random access memory until resistance values of the memory cells in the resistive random access memory reach a second preset value;
wherein the second preset value is less than the resistance values of the memory cells when transitioning from the high resistance state to the low resistance state;
a third input unit, configured to input a plurality of pulses of a third voltage into the resistive random access memory until the resistance values of the memory cells in the resistive random access memory reach a third preset value;
wherein the third preset value is less than the second preset value;
and so on, until an Nth input unit, configured to input a plurality of pulses of an Nth voltage into the resistive random access memory until the resistance values of the memory cells in the resistive random access memory reach an Nth preset value;
wherein N is greater than or equal to 3, voltage values of the first voltage, the second voltage, the third voltage . . . and the Nth voltage gradually decrease, the Nth preset value is less than an (N−1)th preset value, and the Nth preset value is a target resistance value achieved to complete an initialization of the memory cells;
wherein inputting a plurality of pulses of an ith voltage into the resistive random access memory until the resistance values of the memory cells in the resistive random access memory reach an ith preset value comprises:
inputting the plurality of pulses of the ith voltage into the resistive random access memory;
when a total number of the input pulses of the ith voltage is greater than a second preset threshold and a resistance change rate is less than a rate threshold, increasing the ith voltage to obtain an increased ith voltage, and inputting a plurality of pulses of the increased ith voltage into the resistive random access memory until the resistance values of the memory cells in the resistive random access memory reach the ith preset value;
wherein i represents any of two, three . . . N−1, and N.

8 more elements

Dependencies are inferred from the claim text.