Storage device and method of controlling storage device

A method of controlling a storage device including a memory cell including a first conductive layer, a second conductive layer, and a memory layer that is between the first and second conductive layers and can switch between a plurality of states, the states including a first state and a second state in which electrical resistance of the memory layer is higher than in the first state, the method comprising:

• performing a write process by which the states of the memory cell are switched, the write process including a first write process and a second write process,
• the first write process for switching the memory layer from the second state to the first state including alternately applying to the second conductive layer a first pulse having a first voltage of positive polarity and a second pulse having a second voltage of having negative polarity a plurality of times, an absolute value of the second voltage being larger than an absolute value of the first voltage, and a final pulse applied to the second conductive layer in the first write process being the second pulse, and the second write process for switching the memory layer from the first state to the second state including alternately applying to the second conductive layer a third pulse having a third voltage of negative polarity and a fourth pulse having a fourth voltage of positive polarity a plurality of times, an absolute value of the fourth voltage being larger than an absolute value of the third voltage, and a final pulse applied to the second conductive layer in the second write process being the fourth pulse.

A storage device comprising:

• a memory cell comprising a first conductive layer, a second conductive layer, and a memory layer that is between the first and second conductive layers and can switch between a plurality of states, the states including:
• a first state,
• a second state in which electrical resistance of the memory layer is higher than in the first state,
• a third state in which the electrical resistance of the memory layer is higher than in the first state and lower than in the second state, and
• a fourth state in which the electrical resistance of the memory layer is higher than in the third state and lower than in the second state;
• and
• a control circuit configured to execute a write process by which the states of the memory cell are switched, the write process including a first write process, a second write process, a third write process, and a fourth write process, wherein
• the control circuit is configured to:
• in the first write process to switch the memory layer from the second state to the first state, alternately apply to the second conductive layer a first pulse having a first voltage of positive polarity and a second pulse having a second voltage of negative polarity, an absolute value of the second voltage being larger than an absolute value of the first voltage,
• in the second write process to switch the memory layer from the first state to the second state, alternately apply to the second conductive layer a third pulse having a third voltage of negative polarity and a fourth pulse having a fourth voltage of positive polarity, an absolute value of the fourth voltage being larger than an absolute value of the third voltage,
• in the third write process to switch the memory layer from the second state to the third state, alternately apply to the second conductive layer a fifth pulse having a fifth voltage of positive polarity and a sixth pulse having a sixth voltage of negative polarity, an absolute value of the sixth voltage being larger than an absolute value of the fifth voltage, and
• in the fourth write process to switch the memory layer from the first state to the fourth state, alternately apply to the second conductive layer a seventh pulse having a seventh voltage of negative polarity and an eighth pulse having an eighth voltage of positive polarity, an absolute value of the eighth voltage being larger than an absolute value of the seventh voltage.