Memory devices for implementing read operation of bidirectional selector only memory (SOM) cells

A memory device comprising:

• a memory cell array including a plurality of memory cells, each of the plurality of memory cells including a material film, a first electrode on a first side of the material film, and a second electrode on a second side of the material film, wherein a logic state of the material film is programmed based on whether the material film is in a crystalline state or an amorphous state;
• an access circuit configured to apply a first voltage to a first electrode of a selected memory cell from among the plurality of memory cells and apply a second voltage to a second electrode of the selected memory cell;
• and
• a sense circuit configured to determine a logic state of the selected memory cell based on electrical reactions of a first sensing node and a second sensing node connected to the selected memory cell with regard to the first voltage and the second voltage,
• wherein the sense circuit comprises:
• a capacitor connected between the first sensing node and the second sensing node;
• a pre-charger configured to pre-charge a first end of the capacitor to a voltage level of a pre-charge voltage;
• and
• a comparing circuit configured to compare a voltage level of the first end of the capacitor with a voltage level of a reference voltage and output a signal indicating the logic state of the selected memory cell.

A memory device comprising:

• a memory cell array including a plurality of memory cells, each of the plurality of memory cells including a material film, a first electrode on a first side of the material film, and a second electrode on a second side of the material film, wherein a logic state of the material film is programmed based on whether the material film is in a crystalline state or an amorphous state;
• an access circuit configured to apply a first voltage to a first electrode of a selected memory cell from among the plurality of memory cells and apply a second voltage to a second electrode of the selected memory cell;
• and
• a sense circuit configured to determine a logic state of the selected memory cell based on electrical reactions of a first sensing node and a second sensing node connected to the selected memory cell with regard to the first voltage and the second voltage,
• wherein the sense circuit comprises:
• a first capacitor connected between the first sensing node and a sensing input node;
• a second capacitor connected between the second sensing node and the sensing input node;
• a pre-charger configured to pre-charge the sensing input node with a pre-charge voltage based on a pre-charge control signal;
• and
• a comparing circuit configured to compare a voltage level of the sensing input node with a voltage level of a reference voltage and output a signal indicating the logic state of the selected memory cell.