Semiconductor device including ferroelectric memory cell with doped ferroelectric layer
AssigneeSK Hyinx Inc.
InventorJeong Hwan Song
Life of this patent
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Abstract
A semiconductor device may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and exhibits different resistance states for storing data and is structured to be either electrically conductive or electrically non-conductive in response to a voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes a ferroelectric layer exhibiting deep traps for trapping conductive carriers and a first dopant doped in the ferroelectric layer to form shallow traps providing a conductive path for conductive carriers to move in the ferroelectric layer.
Claims13
A semiconductor device having at least one memory cell, the memory cell comprising:
- a first electrode layer;
- a second electrode layer;
- and
- a self-selecting memory layer which is interposed between the first electrode layer and the second electrode layer, exhibits different resistance states for storing data, and is structured to be either electrically conductive or electrically non-conductive in response to a voltage applied to the first and second electrode layers,
- wherein the self-selecting memory layer includes:
- a ferroelectric layer including deep traps configured to trap conductive carriers and to suppress movement of the trapped conductive carriers when a voltage applied to the first and second electrode layers is less than a threshold voltage;
- and
- a first dopant doped in the ferroelectric layer to form shallow traps configured to provide a conductive path for the conductive carriers when the voltage applied to the first and second electrode layers is equal to or greater than the threshold voltage,
- wherein elements included in the first dopant include at least one of aluminum (Al), lanthanum (La), niobium (Nb), vanadium (V), tantalum (Ta), tungsten (W), chromium (Cr), molybdenum (Mo), boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), titanium (Ti), copper (Cu), zirconium (Zr), or hafnium (Hf).
A semiconductor device having at least one memory cell, the at least one memory cell comprising:
- a first electrode layer;
- a second electrode layer;
- and
- a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and being structured to be turned on and off according to movement of conductive carriers between traps in a ferroelectric layer,
- wherein the self-selecting memory layer includes:
- a ferroelectric layer including deep traps configured to trap conductive carriers and to maintain the self-selecting memory layer in a non-conductive state when a voltage applied to the first and second electrode layers is less than a threshold voltage;
- and
- a dopant doped in the ferroelectric layer to form shallow traps configured to receive the conductive carriers released from the deep traps and to enable a conductive state of the self-selecting memory layer when the voltage applied to the first and second electrode layers is equal to or greater than the threshold voltage,
- wherein elements included in the dopant include at least one of aluminum (Al), lanthanum (La), niobium (Nb), vanadium (V), tantalum (Ta), tungsten (W), chromium (Cr), molybdenum (Mo), boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), titanium (Ti), copper (Cu), zirconium (Zr), or hafnium (Hf), and wherein the self-selecting memory layer is turned on when conductive carriers move from the deep traps to the shallow traps, and an amount of the conductive carriers moving from the deep traps to the shallow traps depends on a polarization state of the ferroelectric layer.
Dependencies are inferred from the claim text.