Memory devices with RC tracking and methods for operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien-Yuan Chen, Hau-Tai Shieh, Cheng Hung Lee
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Abstract
A memory circuit includes a memory array comprising a plurality of memory cells arranged over a plurality of word lines and along a bit line, and a controller operatively coupled to the memory array and comprising an RC detector. The RC detector is configured to advance a timing for a first tracking signal to fall, subsequently to a second tracking signal transitioning to rise and prior to a third tracking signal transitioning to rise. The first tracking signal is conducted through a first tracking line, the second tracking signal is provided to conduct through a second tracking line, and the third tracking signal is conducted through the second tracking line.
Claims20
A memory circuit, comprising:
- a memory array comprising a plurality of memory cells;
- and
- a controller operatively coupled to the memory array and comprising an RC detector;
- wherein the RC detector comprises:
- a first transistor that is diode-connected;
- a second transistor;
- and
- a third transistor;
- wherein the first to third transistor are coupled to one another in series;
- wherein the RC detector is configured to adjust a timing of a falling edge of a first tracking signal based on a rising edge of a second tracking signal and a rising edge of a third tracking signal.
A memory circuit, comprising:
- a memory array comprising a plurality of memory cells arranged over a plurality of word lines and along a bit line;
- and
- a controller operatively coupled to the memory array and comprising an RC detector;
- wherein the RC detector comprises:
- a first transistor that is diode-connected;
- a second transistor;
- and
- a third transistor;
- wherein the first to third transistor are coupled to one another in series;
- wherein the RC detector is configured to advance a timing for a first tracking signal to fall, subsequently to a second tracking signal transitioning to rise and prior to a third tracking signal reaching a high logic state;
- wherein the first tracking signal is conducted through a first tracking line, the second tracking signal is provided to conduct through a second tracking line, and the third tracking signal is conducted through the second tracking line.
A method for operating a memory circuit, comprising:
- turning on a first transistor by a first tracking signal provided to conduct through a tracking word line and turning on a second transistor by a second tracking signal to be conducted through the tracking word line;
- advancing a timing to pull down a voltage level present on a tracking bit line;
- turning off the second transistor by the second tracking signal conducted through the tracking word line;
- and
- in response to the voltage level on the tracking bit line falling to a threshold, generating an enable signal to cause a word line signal to fall.
Dependencies are inferred from the claim text.