Low power read circuit for multi-bank memory
AssigneeMedia Tek Singapore Pte. Ltd.
InventorsJaswinder Singh Sidhu, Manish Trivedi, Sumanth Katte Gururajarao, Sagar Y Abachi
Life of this patent
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Abstract
A multi-bank memory includes: a pair of far banks coupled to a first word line and a first pair of local bitlines, respectively; a pair of near banks coupled to a second word line and a second pair of local bitlines, respectively; a far global bit line coupled to the first pair of local bitlines; a first NAND gate having a first input coupled to the second pair of local bitlines and a second input coupled to the far global bit line; a near global bit line coupled to the output of the first NAND gate; and a global input/output (I/O) circuit, coupled to the near global bit line, for outputting data.
Claims7
A multi-bank memory comprising:
- a pair of far banks coupled to a first word line and a first pair of local bitlines, respectively;
- a pair of near banks coupled to a second word line and a second pair of local bitlines, respectively;
- a far global bit line coupled to the first pair of local bitlines;
- a NOR gate having a first input coupled to the second pair of local bitlines and a second input coupled to the far global bit line;
- a near global bit line coupled to the output of the NOR gate;
- and
- a global input/output (I/O) circuit, coupled to the near global bit line, for outputting data;
- wherein during an access operation of the pair of far banks, data on the first pair of local bitlines will be carried on the far global bit line and the near global bit line, and during an access operation of the pair of near banks, data on the second pair of local bitlines will be carried on the near global bit line.
Dependencies are inferred from the claim text.