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US 12,755,778 B2Granted
Memory circuits with keeper circuits and methods for operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMasaya Hamada, Makoto Yabuuchi
Life of this patent
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Abstract
A memory circuit includes a plurality of memory cells commonly coupled to a bit line. The memory circuit includes a pre-charge circuit coupled to the bit line, and comprising one or more first transistors with a first conductive type. The memory circuit includes a keeper circuit coupled to the bit line, and comprising one or more second transistors with a second conductive type.
Claims20
A memory circuit, comprising:
- a plurality of memory cells commonly coupled to a bit line;
- a pre-charge circuit coupled to the bit line, and comprising one or more first transistors with a first conductive type;
- and
- a keeper circuit coupled to the bit line, and comprising one or more second transistors with only a second conductive type.
1 more element
A memory circuit, comprising:
- a plurality of memory cells commonly coupled to a bit line;
- a pre-charge circuit coupled to the bit line and configured to pre-charge the bit line to a high logic state, while none of the plurality of memory cells is being read or written, wherein the pre-charge circuit comprises at least one p-type transistor;
- and
- a keeper circuit coupled to the bit line and configured to keep a voltage level present on the bit line substantially close to a first voltage level when at least one of the plurality of memory cells storing a high logic state that corresponds to the first voltage level is being read, and substantially close to a second voltage level when at least one of the plurality of memory cells storing a low logic state that corresponds to the second voltage level is being read, wherein the keeper circuit comprises at least one n-type transistor, wherein the at least one n-type transistor is the only conductive type of transistor in the keeper circuit.
1 more element
A method, comprising:
- pre-charging a bit line coupled to a plurality of memory cells to a first logic state by a pre-charge circuit;
- and
- keeping a voltage level present on the bit line substantially close to a first voltage level by a keeper circuit comprising at least one transistor of only a first conductive type when at least a first one of the plurality of memory cells storing the first logic state that corresponds to the first voltage level is being read, and keeping the voltage level substantially close to a second voltage level by the keeper circuit when at least a second one of the plurality of memory cells storing a second logic state that corresponds to the second voltage level is being read.
Dependencies are inferred from the claim text.