US 12,755,777 B2Granted

CMOS memory cell for high voltage applications

AssigneeMicrosemi SoC Corporation

InventorVictor Nguyen

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Abstract

A memory cell comprises a plurality of n-type metal oxide semiconductor (NMOS) transistors and a plurality of p-type metal oxide semiconductor (PMOS) transistors. First and second NMOS transistors are electrically connected to one another in a cross-coupled configuration. First and second PMOS transistors are electrically connected to one another in a cross-coupled configuration. Third and fourth NMOS transistors are electrically connected to the first and second NMOS transistors in a cascode configuration. Third and fourth PMOS transistors are electrically connected to the first and second PMOS transistors in a cascode configuration. A fifth PMOS transistor includes a drain, a gate, and a source, wherein the drain is electrically connected to a gate of the second PMOS transistor and a drain of the first PMOS transistor, and the source is electrically connected to a gate of the first PMOS transistor and a drain of the second PMOS transistor.

Claims20

Dependent claims

A memory cell comprising:

first and second n-type metal oxide semiconductor (NMOS) transistors electrically connected to one another in a cross-coupled configuration;
first and second p-type metal oxide semiconductor (PMOS) transistors electrically connected to one another in a cross-coupled configuration;
third and fourth NMOS transistors, wherein a gate of the third NMOS transistor is electrically connected to a gate of the fourth NMOS transistor, a source of the third NMOS transistor is electrically connected in a cascode configuration to a drain of the first NMOS transistor, and a source of the fourth NMOS transistor is electrically connected in a cascode configuration to a drain of the second NMOS transistor;
third and fourth PMOS transistors, wherein a gate of the third PMOS transistor is electrically connected to a gate of the fourth PMOS transistor, a source of the third PMOS transistor is electrically connected in a cascode configuration to a drain of the first PMOS transistor, and a source of the fourth PMOS transistor is electrically connected in a cascode configuration to a drain of the second PMOS transistor;
and
a fifth PMOS transistor, a drain of the fifth PMOS transistor electrically connected to a gate of the second PMOS transistor and a drain of the first PMOS transistor, and a source of the fifth PMOS transistor electrically connected to a gate of the first PMOS transistor and a drain of the second PMOS transistor.

3 more elements

A memory cell comprising:

first and second n-type metal oxide semiconductor (NMOS) transistors electrically connected to one another in a cross-coupled configuration, the first and second NMOS transistors respectively including a source that is electrically connected to an electrical common point;
first and second p-type metal oxide semiconductor (PMOS) transistors electrically connected to one another in a cross-coupled configuration, the first and second PMOS transistors respectively including a drain that is electrically connected to a voltage supply having a voltage ranging from approximately 0.84 Volts to approximately 1.4 Volts;
third and fourth NMOS transistors, wherein a gate of the third NMOS transistor is electrically connected to a gate of the fourth NMOS transistor, a source of the third NMOS transistor is electrically connected in a cascode configuration to a drain of the first NMOS transistor, and a source of the fourth NMOS transistor is electrically connected in a cascode configuration to a drain of the second NMOS transistor;
third and fourth PMOS transistors, wherein a gate of the third PMOS transistor is electrically connected to a gate of the fourth PMOS transistor, a source of the third PMOS transistor is electrically connected in a cascode configuration to a drain of the first PMOS transistor, and a source of the fourth PMOS transistor is electrically connected in a cascode configuration to a drain of the second PMOS transistor;
a fifth PMOS transistor, a drain of the fifth PMOS transistor electrically connected to a gate of the second PMOS transistor and a drain of the first PMOS transistor, and a source of the fifth PMOS transistor electrically connected to a gate of the first PMOS transistor and a drain of the second PMOS transistor;
and
fifth and sixth NMOS transistors, wherein
a source of the fifth NMOS transistor is electrically connected to the drain of the first NMOS transistor, the source of the third NMOS transistor, and the gate of the second NMOS transistor,
a source of the sixth NMOS transistor is electrically connected to the drain of the second NMOS transistor, the source of the fourth NMOS transistor, and the gate of the first NMOS transistor,
a drain of the fifth NMOS transistor is electrically connected to a bit line bar electronic signal,
a drain of the sixth NMOS transistor is electrically connected to a bit line electronic signal, and
a gate of the fifth NMOS transistor and a gate of the sixth NMOS transistor respectively are electrically connected to a first word line electronic signal.

9 more elements

Dependencies are inferred from the claim text.