Memory comprising command decoding circuit and control circuit
AssigneeCXMT Corporation
InventorYinchuan Gu
Life of this patent
Estimating the term…
Abstract
A memory is provided in this application, including multiple group regions, a command decoding circuit, and a control circuit. Each group region includes multiple bank groups, and each bank group corresponds to one bank group address. An active instruction is received by the command decoding circuit, and the active instruction is decoded to obtain an active command signal. The bank group address, a row address, and the active command signal are received by the control circuit, and the row address is sent to one of the group regions based on the active command signal and the bank group address.
Claims12
A memory, comprising a plurality of group regions, a command decoding circuit, and a control circuit;
- each group region comprising a plurality of bank groups, and each bank group corresponding to one bank group address;
- the command decoding circuit receiving an active instruction, and decoding the active instruction to obtain an active command signal;
- and
- the control circuit receiving the bank group address, a row address, and the active command signal, and sending the row address to one of the group regions based on the active command signal and the bank group address;
- wherein the control circuit is configured to:
- send the row address to the one of the group regions based on the active command signal and at least one target bit of the bank group address;
- the target bit of the bank group address being a same address bit as a corresponding address bit in any other bank group address in the group region.
A memory, comprising a plurality of group regions, a command decoding circuit, and a control circuit;
- each group region comprising a plurality of bank groups, and each bank group corresponding to one bank group address;
- the command decoding circuit receiving an active instruction, and decoding the active instruction to obtain an active command signal;
- and
- the control circuit receiving the bank group address, a row address, and the active command signal, and sending the row address to one of the group regions based on the active command signal and the bank group address;
- wherein the memory further comprising:
- a window signal circuit, connected to the command decoding circuit and configured to receive the active command signal, the bank group address, and a bank address, and activate, based on the active command signal, the bank group address, and the bank address, a bank corresponding to the bank group address and the bank address.
Dependencies are inferred from the claim text.