Semiconductor device having row decoder circuit

An apparatus comprising:

• a memory cell array configured to be accessed by a plurality of main word signals;
• a main word circuit configured to activate one of the plurality of main word signals and arranged in a main word circuit region overlapping with the memory cell array in a first direction
• a sense circuit configured to amplify a read data read from the memory cell array and arranged in a sense amplifier region overlapping with the memory cell array in a second direction perpendicular to the first direction;
• and
• a voltage control circuit configured to control an operation voltage of the main word circuit,
• wherein a part of the voltage control circuit is arranged in the main word circuit region so as to overlap with the memory cell array in the first direction, and
• wherein another part of the voltage control circuit is arranged in a gap region adjacent to the main word circuit region in the second direction and adjacent to the sense amplifier region in the first direction so as not to overlap with the memory cell array in the first direction,
• wherein the voltage control circuit includes:
• a plurality of first power circuits configured to supply the operation voltage having a first level to the main word circuit;
• and
• a second power circuit configured to supply the operation voltage having a second level lower than the first level to the main word circuit,
• wherein one of the plurality of first power circuits is arranged in the main word circuit region,
• wherein another of the plurality of first power circuits is arranged in the gap region
• wherein the voltage control circuit further includes a control circuit configured to activate the first power circuit or the second power circuit, and
• wherein the control circuit is arranged in the main word circuit region.

An apparatus comprising:

• a plurality of first regions arranged in line, each of the plurality of first regions including a second region in a center area, a third region along a first side and a fourth region along a second side opposed to the first sides wherein the third region of a first one of the plurality of first regions and the third region of a second one of the plurality of first regions are integrated with each other to form a combined region, wherein the first one of the plurality of first regions is adjacent to the second one of the plurality of first regions;
• a plurality of main word driver circuits each arranged in a corresponding one of second regions of the plurality of first regions;
• and
• a voltage control circuit configured to supply a voltage to each of the plurality of main word driver circuits, the voltage control circuit is divided into multiple circuit portions which are arranged in one or ones of the third and fourth regions in one or ones of the plurality of first regions.

An apparatus comprising:

• a plurality of first regions arranged in line, each of the plurality of first regions including a second region in a center area, a third region along a first side and a fourth region along a second side opposed to the first side;
• a plurality of main word driver circuits each arranged in a corresponding one of second regions of the plurality of first regions;
• and
• a voltage control circuit configured to supply a voltage to each of the plurality of main word driver circuits, the voltage control circuit is divided into multiple circuit portions which are arranged in one or ones of the third and fourth regions in one or ones of the plurality of first regions,
• wherein the third region is only available for a first conductivity type transistor, and
• wherein the fourth region is only available for a second conductivity type transistor.