3D NOR flash based in-memory computing

A method for multiplying a signed input bit by a signed coefficient bit in a memory array including word lines and bit lines, including:

• storing respective threshold levels VT1, VT2, VT3 and VT4 in first, second, third and fourth memory cells to represent the signed coefficient bit, wherein the first memory cell is on a first bit line and a first word line, the second memory cell is on a second bit line and the first word line, the third memory cell is on the first bit line and a second word line, and the fourth memory cell is on the second bit line and the second word line;
• applying, during an in-memory computation process, respective word line voltages VWL0, VWL1 to the first and second word lines to represent the signed input bit;
• and
• sensing a difference in respective currents IBL0 and IBL1 on the first and second bit lines, including determining a sign of the difference by comparing one of currents IBL0 and IBL1 to a reference current, and determining a magnitude of the difference including selecting one of currents IBL0 and IBL1 in dependence on the sign and comparing the selected one of the currents to a sequence of reference currents.