Sense amplifiers and operation methods thereof, and memory devices including the same

An operation method of a sense amplifier connected to a bit line and a complementary bit line, the operation method comprising:

• performing a first precharge operation for the bit line and the complementary bit line;
• performing a first sensing operation for the bit line and the complementary bit line precharged based on the first precharge operation;
• in response to a voltage level of the bit line changing to a first voltage level based on the first sensing operation, performing a first program operation for a first transistor connected to one of the bit line and the complementary bit line;
• performing a second precharge operation for the bit line and the complementary bit line;
• performing a second sensing operation for the bit line and the complementary bit line precharged based on the second precharge operation;
• in response to the voltage level of the bit line changing to the first voltage level based on the second sensing operation, performing a second program operation for the first transistor;
• and
• in response to the voltage level of the bit line changing to a second voltage level different from the first voltage level based on the second sensing operation, ceasing performing program operations for the first transistor.

A memory device comprising:

• a memory cell array connected to a bit line and a complementary bit line;
• and
• a sense amplifier connected to the bit line through a first conductive line and connected to the complementary bit line through a second conductive line having a different length from the first conductive line,
• wherein the sense amplifier includes:
• first and second transistors connected in series between the first conductive line and the second conductive line and having a first channel type;
• third and fourth transistors connected in series between the first conductive line and the second conductive line and having a second channel type;
• and
• a fifth transistor connected between a gate terminal of the first transistor and the second conductive line,
• wherein threshold voltages of the first and second transistors are different from each other.