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US 12,755,714 B2Granted
Data integrated circuit including latch controlled by clock signal and display device including the same
AssigneeSamsung Display Co., Ltd.
InventorsWontae Kim, Sooyeon Kim, Young-Il Ban, Sunkyu Son
Life of this patent
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Abstract
Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.
Claims18
A display device comprising:
- a plurality of pixels connected to a plurality of data lines;
- a data driving circuit configured to output a plurality of data voltages to the plurality of data lines in response to a main clock signal and a clock signal;
- and
- a timing controller configured to output a plurality of image signals, the main clock signal, a delay signal and the clock signal,
- wherein the data driving circuit comprises:
- a shift register configured to output a plurality of latch clock signals that are sequentially activated in response to the clock signal;
- a latch circuit configured to latch the plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals;
- an output circuit configured to convert the plurality of digital image signals to the plurality of data voltages;
- and
- a clock generator configured to receive the main clock signal and the delay signal, divide the main clock signal to generate the plurality of latch output signals, and output a first latch output signal and a second latch output signal among the plurality of latch output signals,
- wherein the clock generator adjusts a phase difference between the plurality of latch output signals in response to the delay signal,
- wherein the latch circuit comprises:
- a first latch group configured to latch a first subset of the plurality of image signals based on a first subset of the latch clock signals and output a plurality of first digital image signals of the plurality of digital image signals in response to the first latch output signal during a first period within one horizontal period;
- and
- a second latch group configured to latch a second subset of the plurality of image signals based on a second subset of the latch clock signals and output a plurality of second digital image signals of the plurality of digital image signals in response to the second latch output signal during a second period within the same one horizontal period, and
- wherein the first period is not overlapped with the second period.
13 more elements
An electronic device comprising:
- a plurality of pixels connected to a plurality of data lines;
- a data driving circuit configured to output a plurality of data voltages to the plurality of data lines in response to a main clock signal and a clock signal;
- and
- a timing controller configured to output a plurality of image signals, the main clock signal, a delay signal and the clock signal,
- wherein the data driving circuit comprises:
- a latch circuit configured to latch the plurality of image signals in response to a plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals;
- an output circuit configured to convert the plurality of digital image signals to the plurality of data voltages;
- and
- a clock generator configured to receive the main clock signal and the delay signal, divide the main clock signal to generate the plurality of latch output signals, and output a first latch output signal and a second latch output signal among the plurality of latch output signals,
- wherein the clock generator adjusts a phase difference between the plurality of latch output signals in response to the delay signal,
- wherein the latch circuit comprises:
- a first latch group configured to latch a first subset of the plurality of image signals based on a first subset of the latch clock signals and output a plurality of first digital image signals of the plurality of digital image signals in response to the first latch output signal during a first period within one horizontal period;
- and
- a second latch group configured to latch a second subset of the plurality of image signals based on a second subset of the latch clock signals and output a plurality of second digital image signals of the plurality of digital image signals in response to the second latch output signal during a second period within the same one horizontal period, and
- wherein the first period is not overlapped with the second period.
12 more elements
An electronic device comprising:
- a controller configured to output a plurality of control signals;
- and
- a display module configured to display an image in response to the plurality of control signals,
- wherein the display module comprises:
- a plurality of pixels connected to a plurality of data lines;
- a timing controller configured to output a plurality of image signals, a main clock signal, a delay signal and a clock signal;
- and
- a data driving circuit configured to output a plurality of data voltages to the plurality of data lines in response to the plurality of image signals, the main clock signal and the clock signal;
- and
- wherein the data driving circuit comprises:
- a latch circuit configured to latch the plurality of image signals in response to a plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals;
- an output circuit configured to convert the plurality of digital image signals to the plurality of data voltages;
- and
- a clock generator configured to receive the main clock signal and the delay signal, divide the main clock signal to generate the plurality of latch output signals, and output a first latch output signal and a second latch output signal among the plurality of latch output signals,
- wherein the clock generator adjusts a phase difference between the plurality of latch output signals in response to the delay signal,
- wherein the latch circuit comprises:
- a first latch group configured to latch a first subset of the plurality of image signals based on a first subset of the latch clock signals and output a plurality of first digital image signals of the plurality of digital image signals in response to the first latch output signal during a first period within one horizontal period;
- and
- a second latch group configured to latch a second subset of the plurality of image signals based on a second subset of the latch clock signals and output a plurality of second digital image signals of the plurality of digital image signals in response to the second latch output signal during a second period within the one horizontal period, and
- wherein the first period is not overlapped with the second period.
17 more elements
Dependencies are inferred from the claim text.