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US 12,755,675 B2Granted
System and method for reducing power consumed by a display
AssigneeGoogle Inc.
InventorsBo Li, Edwin Lyle Hudson
Life of this patent
Estimating the term…
Abstract
A word line regulator that can control an SRAM cell during a write process is disclosed. The SRAM cell is coupled to bit lines that are driven using a reduced voltage in order to conserve power. The SRAM cell includes a latch that is powered by a power supply in a power domain that is different from the bit lines. The word line regulator is configured to output a voltage that is based on the different power domains to ensure the proper operation of transistors in the SRAM cell during the write process.
Claims20
A pixel for a display, the pixel comprising:
- a latch circuit powered by an upper rail voltage and a lower rail voltage;
- a first bit line coupled to a first output of the latch circuit by a first transistor, the first transistor controlled in a ON condition during a write operation by a word line voltage on a word line and a LOW bit line voltage on the first bit line;
- a second bit line coupled to a second output of the latch circuit by a second transistor, the second transistor controlled in an OFF condition during the write operation by the word line voltage and a HIGH bit line voltage on the second bit line;
- and
- a word line regulator configured to receive the HIGH bit line voltage as a reference input, and dynamically track the HIGH bit line voltage in real-time, and control the word line voltage on the word line to float above the dynamically tracked HIGH bit line voltage on the second bit line by a threshold voltage to limit a current conducted by the second transistor in the OFF condition during the write operation.
2 more elements
A method for writing to a memory cell of a pixel array, the method comprising:
- driving a first bit line to a lower rail voltage of the memory cell, the first bit line coupled to a first output of a latch circuit via a first transistor, the first transistor coupled at a first gate terminal to a word line;
- driving a second bit line to a HIGH bit line voltage, the second bit line coupled to a second output of the latch circuit via a second transistor, the second transistor coupled at a second gate terminal to the word line;
- receiving the HIGH bit line voltage at a word line regulator coupled to the pixel array and dynamically tracking the HIGH bit line voltage in real-time;
- controlling the word line to float above the dynamically tracked HIGH bit line voltage by a threshold voltage using the word line regulator;
- coupling the word line to the word line regulator so that the first transistor is biased in an ON condition to couple the lower rail voltage to the first output of the latch circuit and so that the second transistor is biased to limit a current at the second output of the latch circuit;
- and
- configuring the latch circuit to output an upper rail voltage of the memory cell to the second output based on the first output being coupled to the lower rail voltage.
4 more elements
A pixel for a display comprising:
- a word line;
- a first bit line driven at a HIGH bit line voltage or a lower rail voltage;
- a second bit line driven at the lower rail voltage when the first bit line is driven at the HIGH bit line voltage and driven at the HIGH bit line voltage when the first bit line is driven at the lower rail voltage;
- a latch circuit configured to output an upper rail voltage or the lower rail voltage;
- a first transistor connected at a first drain terminal to the latch circuit, connected at a first source terminal to the first bit line, and connected at a first gate terminal to the word line;
- a second transistor connected at a second drain terminal to the latch circuit, connected at a second source terminal to the second bit line, and connected at a second gate terminal to the word line;
- and
- a word line regulator configured to receive the HIGH bit line voltage, dynamically track the HIGH bit line voltage in real-time, and generate a word line voltage on the word line that floats above the dynamically tracked HIGH bit line voltage by a reference voltage, the HIGH bit line voltage being less than the upper rail voltage.
5 more elements
Dependencies are inferred from the claim text.