Chips supporting constant time program control of nested loops

A chip, comprising:

• at least one arithmetic-logic computing unit;
• and
• a controller operatively coupled to the at least one arithmetic-logic computing unit, wherein:
• the controller is configured according to a program configuration, the program configuration comprising at least one inner loop and at least one outer loop, wherein the at least one outer loop comprises an infinite loop,
• the controller is configured to cause the at least one arithmetic computing unit to execute a plurality of operations according to the program configuration, the plurality of operations comprising an operation associated with the at least one inner loop, the controller being configured to cause the at least one arithmetic computing unit to execute the operation during a first clock cycle,
• the controller is configured to maintain at least a first loop counter and a second loop counter, the first loop counter configured to count a number of executed iterations of the infinite loop, and the second loop counter configured to count a number of executed iterations of the at least one inner loop,
• the controller is configured to provide, during the first clock cycle, a first indication of whether the first loop counter corresponds to a last iteration and a second indication of whether the second loop counter corresponds to a last iteration,
• the controller is configured to alternatively increment or maintain the first loop counter during the first clock cycle according to the first indication,
• the controller is configured to alternatively increment or reset the second loop counter during the first clock cycle according to the second indication,
• the controller is configured to maintain a program counter, the program counter indicating a current operation of the plurality of operations, and
• the controller is configured to provide a third indication of whether the current operation is a final operation of the inner loop.