Secure control flow prediction

An integrated circuit comprising:

• a processor core configured to execute instructions;
• an instruction decode buffer configured to store instructions fetched from memory;
• and
• a control flow predictor with entries that include branch target addresses associated with instructions stored in the instruction decode buffer, wherein the branch target addresses are predictions, and wherein the integrated circuit is configured to:
• access a first entry of the entries that is associated with an instruction stored in the instruction decode buffer, wherein the first entry includes a first branch target address;
• compare a context tag associated with the first entry to a context identifier associated with a currently executing process, wherein the context identifier corresponds to a first world identifier stored in a data store;
• and
• responsive to a mismatch between the context tag and the context identifier, provide an alternate value in place of the first branch target address, wherein the alternate value is configured to cause an exception that applies a constraint on speculative execution for the instruction, wherein the constraint prevents the speculative execution from modifying data stored in a cache of the integrated circuit prior to validation of a prediction for the instruction;
• wherein the processor core is configured to tag memory requests with the first world identifier, and wherein the integrated circuit further comprises world identifier checker circuitry configured to check the first world identifier to determine authorization to access a portion of memory space addressed by the memory requests.

A method comprising:

• accessing a first entry among entries in a control flow predictor, wherein the first entry includes a first branch target address associated with an instruction stored in an instruction decode buffer, wherein the first branch target address is a prediction;
• comparing a context tag associated with the first entry to a context identifier associated with a currently executing process, wherein the context identifier corresponds to a first world identifier;
• tagging, by a processor core executing the currently executing process, memory requests with the first world identifier to confirm authorization to access a portion of memory space addressed by the memory requests;
• checking, by world identifier checker circuitry, the first world identifier against a stored world identifier to determine authorization to access the portion of memory space;
• and
• responsive to a mismatch between the context tag and the context identifier, providing an alternate value in place of the first branch target address, wherein the alternate value is configured to cause an exception that applies a constraint on speculative execution for an instruction, wherein the constraint prevents the speculative execution from modifying data stored in a cache of an integrated circuit prior to validation of a prediction for the instruction.