Floating point multiplications

A hardware accelerator comprising:

• a compute-in-memory (CIM) macro configured to perform a vector matrix multiplication (VMM) operation between a vector of activation values and a matrix of weight values;
• and
• a mode decoding unit configured to provide an arithmetic mode of the VMM operation according to a first floating point format of the activation values and a second floating point format of the weight values, the first floating point format and the second floating point format being flexible,
• wherein a column cell of the CIM macro is configured to output a primitive product between an activation value and a weight value and comprises:
• a half adder configured to add an exponent bit of the activation value and an exponent bit of the weight value and output a carry-out bit and a sum bit;
• a first multiplexer configured to select zero or a prior stage carry-out bit from a prior stage half adder and output a first selection to a full adder;
• a second multiplexer configured to select zero or the sum bit and output a second selection to the full adder;
• and
• a third multiplexer configured to select zero or a carry-in bit from a prior stage full adder and output a third selection to the full adder,
• wherein the first multiplexer, the second multiplexer and the third multiplexer perform respective selections based on control signals according to the arithmetic mode.