Debugging system method using universal asynchronous receiver/transmitter (UART) interface by switching between USB or ethernet interface for data transmission requirement

A method for interface management, comprising:

• providing a main processor, wherein the main processor comprises a UART interface and an auxiliary interface;
• transmitting a control signal through the main processor;
• providing a switch and a first sub-circuit, wherein the first sub-circuit comprises a first sub-interface;
• conducting a transmission path between the UART interface and the first sub-interface through the switch according to the control signal,
• wherein a step of conducting the transmission path between the UART interface and the first sub-interface according to the control signal comprises:
• in response to the main processor being in an initial phase, generating, through the main processor, the control signal for conduction, and conducting the transmission path, wherein the transmission path is used for a debug requirement;
• or
• in response to the main processor leaving the initial phase, generating, through the main processor, the control signal for conduction, and conducting the transmission path, wherein the transmission path is used for a data transmission requirement, and using the auxiliary interface for the debug requirement;
• or
• in response to detecting the data transmission requirement, generating, through the main processor, the control signal for conduction, and conducting the transmission path, wherein the transmission path is used for the debug requirement, and using the auxiliary interface for the data transmission requirement.

A system for interface management, comprising:

• a main processor comprising a UART interface;
• a switching circuit coupled to the UART interface;
• a first sub-circuit coupled to the switching circuit, wherein the first sub-circuit comprises a first sub-interface;
• a second circuit coupled to the switching circuit, wherein the second circuit comprises a second sub-interface, wherein
• the switching circuit conducts a first transmission path between the UART interface and the first sub-interface according to a first control signal, or conducts a second transmission path between the UART interface and the second sub-interface;
• and
• an auxiliary interface coupled to the switching circuit, wherein the auxiliary interface is not a UART interface, wherein
• in response to the main processor being in an initial phase, the main processor generates the control signal for conduction and conducts the first transmission path, wherein the first transmission path is used for a debug requirement;
• or
• in response to the main processor leaving the initial phase, the auxiliary interface is used for the debug requirement and the main processor generates the control signal for conduction and conducts the first transmission path, wherein the first transmission path is used for a data transmission requirement;
• or
• in response to detecting the data transmission requirement, the auxiliary interface is used for the data transmission requirement and the main processor generates the control signal for conduction and conducts the first transmission path, wherein the first transmission path is used for the debug requirement.