Network processing using fixed-function logic components close-coupled with programmable logic and software

Enacted on a network interface card comprising a composable processing pipeline, a method for network processing, the method comprising:

• performing a first composed processing pipeline, comprising:
• selecting, using a compute complex component, a programmable per-op component for performing a first function of the first composed processing pipeline;
• and
• controlling, using the compute complex component, the programmable per-op component to perform the first function;
• and
• performing a second composed processing pipeline, comprising:
• selecting, using the compute complex component, a fixed-function logic per-op component for performing a second function of the second composed processing pipeline, wherein the fixed-function logic per-op component is configurable with programmable logic and software running on the compute complex component;
• and
• controlling, using the compute complex component, the fixed-function logic per-op component to perform the second function, wherein the programmable per-op component and the fixed-function logic per-op component provide functions for processing headers and metadata for network packets, wherein the first composed processing pipeline is performed by bypassing the fixed-function logic per-op component, and wherein the second composed processing pipeline is performed by bypassing the programmable per-op component.

A network interface card comprising an integrated circuit device for network processing, the network interface card comprising:

• a composable processing pipeline comprising:
• a field-programmable gate array (FPGA) per-op component;
• and
• an application-specific integrated circuit (ASIC) per-op component, wherein the FPGA per-op component and the ASIC per-op component provide functions for processing headers and metadata for network packets;
• and
• a compute complex component comprising processing circuitry implementing software for controlling the FPGA per-op component and the ASIC per-op component, wherein:
• for a first composed processing pipeline, the processing circuitry is configured to perform a first function using the FPGA per-op component while bypassing the ASIC per-op component;
• and
• for a second composed processing pipeline, the processing circuitry is configured to perform a first function using the ASIC per-op component while bypassing the FPGA per-op component.