Computer device, data processing method, and computer system for performing persistent storage on data

A data processing method applied to a computer device having a central processing unit (CPU) including a logic controller, at least one management chip having an enabled state and a disabled state, and at least two persistent memories, wherein the at least two persistent memories are operatively coupled to the CPU by the at least one management chip, the at least two persistent memories do not require an input/output (IO) interface operation for accessing the at least two persistent memories, a communication state between each of the at least two persistent memories and the CPU is independently controlled by the at least one management chip, and each persistent memory is configured to perform persistent storage on data, the method comprising:

• receiving, by the CPU, a data processing request;
• controlling, by the logic controller, the at least one management chip to control the communication state between each persistent memory and the CPU via the at least one management chip;
• accessing, by the CPU and based on the data processing request, a target persistent memory in the at least two persistent memories and in communication with the CPU;
• and
• reading data from the target persistent memory or writing data to the target persistent memory, wherein
• in response to the at least one management chip between one of the at least two persistent memories and the CPU being in the enabled state, the persistent memory is in communication with the CPU, and
• in response to any management chip between one of the at least two persistent memories and the CPU being in the disabled state, the persistent memory is not in communication with the CPU.

A computer system, comprising:

• a first computer device, wherein the first computer device comprises;
• a central processing unit (CPU) including a logic controller;
• at least one management chip having an enabled state and a disabled state;
• and
• at least two persistent memories operatively coupled to the CPU by the at least one management chip, wherein the at least two persistent memories do not require an input/output (IO) interface operation for accessing the at least two persistent memories,
• each of the at least two persistent memories is configured to perform persistent storage on data,
• the at least one management chip is configured to independently control a communication state between each persistent memory and the CPU,
• the logic controller is configured to control the at least one management chip to control the communication state between each persistent memory and the CPU via the at least one management chip;
• in response to the at least one management chip between one of the at least two persistent memories and the CPU being in the enabled state, the persistent memory is in communication with the CPU,
• in response to any management chip between one of the at least two persistent memories and the CPU being in the disabled state, the persistent memory is not in communication with the CPU, and
• the CPU is configured to access any one of the at least two persistent memories in communication with the CPU;
• and
• a second computer device, wherein the second computer device comprises:
• a CPU including a logic controller;
• at least one management chip having the enabled state and the disabled state;
• and
• at least two persistent memories operatively coupled to the CPU by the at least one management chip, wherein the at least two persistent memories do not require an IO interface operation for accessing the at least two persistent memories,
• each of the at least two persistent memories is configured to perform persistent storage on data,
• the at least one management chip is configured to independently control a communication state between each persistent memory and the CPU,
• the logic controller is configured to control the at least one management chip to control the communication state between each persistent memory and the CPU via the at least one management chip;
• in response to the at least one management chip between one of the at least two persistent memories and the CPU being in the enabled state, the persistent memory is in communication with the CPU,
• in response to any management chip between one of the at least two persistent memories and the CPU being in the disabled state, the persistent memory is not in communication with the CPU, and
• the CPU is configured to access any one of the at least two persistent memories in communication with the CPU, wherein
• the first computer device is configured to send data to the second computer device, and
• the second computer device is configured to store the data, received from the first computer device, in a persistent memory of the second computer device.