Memory device, memory controller, and storage device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJungho Park, Beomkyu Shin, Myungkyu Kim
Life of this patent
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Abstract
A memory device includes a memory cell array including a first memory region storing first data, a page buffer including a first latch configured to store data dumped from the memory cell array, and a control logic circuit configured to receive parity adjustment information from an external device and control an operation of the memory cell array. The first data includes first user data and first parity data including parity bits generated based on the first user data, and the control logic circuit dumps first parity data of which a size is adjusted based on the parity adjustment information to the first latch.
Claims17
A memory device comprising:
- a memory cell array including a first memory region storing first data;
- a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array;
- and
- a control logic circuit configured to receive parity adjustment information from an external device and control an operation of the memory cell array,
- wherein the first data includes first user data and first parity data including parity bits generated based on the first user data,
- wherein the control logic circuit is configured to adjust a size of the first parity data, based on the parity adjustment information, and dump the adjusted first parity data to the first latch, and
- wherein the size of the first parity data dumped to the first latch varies depending on a format of the first parity data indicated by the parity adjustment information.
A storage device comprising:
- a memory device configured to adjust a size of first parity data, based on parity adjustment information, and output the first parity data having the adjusted size;
- and
- a memory controller configured to control an operation of the memory device,
- wherein the memory device includes:
- a memory cell array including a plurality of memory regions;
- a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array;
- and
- a control logic circuit configured to receive the parity adjustment information from the memory controller and control an operation of the memory cell array, and
- wherein the memory controller includes:
- a parity controller including reliability information which includes information indicating reliability of the plurality of memory regions included in the memory device, and the parity controller configured to:
- determine a format and the size of the first parity data, based on the reliability information of a memory region in which user data corresponding to the first parity data is to be stored, and
- provide the parity adjustment information indicating the determined format and size of the first parity data to the memory device.
Dependencies are inferred from the claim text.