Decoder circuit, flash memory controller, and decoding method

A decoding method of a decoder circuit, comprising:

• providing a channel value memory for receiving and storing an input data as a channel value, the channel value being stored in the channel value memory as a codeword, the channel value memory being configured to use multiple consecutive addresses to store multiple bit chunks of the codeword;
• using a variable node unit to generate a posterior probability value and a variable-to-check message based on a specific bit chunk of the channel value and to update the posterior probability value and the variable-to-check message according to a check-to-variable message generated by a check node unit;
• converting the variable-to-check message from a variable node domain to a check node domain to generate a converted variable-to-check message;
• using the check node unit to generate the check-to-variable message according to the converted variable-to-check message;
• converting the check-to-variable message from the check node domain to the variable node domain to generate a converted check-to-variable message to the variable node unit;
• using a decision unit to determine whether to flip at least one bit of the specific bit chunk based on the posterior probability value;
• determining whether to ignore and skip a decoding calculation corresponding to the specific bit chunk in at least one subsequent iterative decoding operation based on whether a decoding calculation result corresponding to the specific bit chunk satisfies a specific condition;
• in a default setting, sequentially outputting the multiple consecutive addresses to the channel value memory to control the channel value memory to sequentially output the multiple bit chunks to the variable node unit in an iterative decoding operation, to make the variable node unit respectively and sequentially perform decoding calculations for the multiple bit chunks;
• and
• when the decoding calculation result of the specific chunk satisfies a specific condition, ignoring and skipping an output of a specific address corresponding to the specific bit chunk in the at least one subsequent iterative decoding operation so as to control the channel value memory to not output the specific bit chunk to the variable node unit in the at least one subsequent iterative decoding operation to make the variable node unit ignore and skip the decoding calculation for the specific bit chunk in the at least one subsequent iterative decoding operation.

A flash memory controller, comprising:

• an encoder, for performing a encoding operation upon a write data sent from a host device to write the write data into a flash memory;
• and
• a decoder circuit, for performing a decoding operation upon a read data read out from the flash memory to generate a decoded read data;
• wherein the decoder circuit comprises:
• a channel value memory, for receiving and storing an input data as a channel value, the channel value being stored in the channel value memory as a codeword, the channel value memory being configured to use multiple consecutive addresses to store multiple bit chunks of the codeword;
• a variable node unit, coupled to the channel value memory, for generating a posterior probability value and a variable-to-check message based on a specific bit chunk of the channel value and for updating the posterior probability value and the variable-to-check message according to a check-to-variable message generated by a check node unit;
• a first barrel shifter, coupled to the variable node unit, for converting the variable-to-check message from a variable node domain to a check node domain to generate a converted variable-to-check message;
• the check node unit, coupled to the first barrel shifter, for generating the check-to-variable message according to the converted variable-to-check message;
• a second barrel shifter, coupled to the check node unit, for converting the check-to-variable message from the check node domain to the variable node domain to generate a converted check-to-variable message to the variable node unit;
• a decision unit, coupled to the variable node unit, for determining whether to flip at least one bit of the specific bit chunk based on the posterior probability value;
• and
• a strategy unit, coupled to the channel value memory, the variable node unit, the decision unit, and the check node unit, for determining whether to ignore and skip a decoding calculation corresponding to the specific bit chunk in at least one subsequent iterative decoding operation based on whether a decoding calculation result corresponding to the specific bit chunk satisfies a specific condition;
• wherein, in a default setting, the strategy unit sequentially outputs the multiple consecutive addresses to the channel value memory to control the channel value memory to sequentially output the multiple bit chunks to the variable node unit in an iterative decoding operation, so that the variable node unit respectively and sequentially performs decoding calculations for the multiple bit chunks;
• when the decoding calculation result of the specific chunk satisfies a specific condition, the strategy unit ignores and skips an output of a specific address corresponding to the specific bit chunk in the at least one subsequent iterative decoding operation so as to control the channel value memory to not output the specific bit chunk to the variable node unit in the at least one subsequent iterative decoding operation to make the variable node unit ignore and skip the decoding calculation for the specific bit chunk in the at least one subsequent iterative decoding operation.