US 12,754,798 B2Granted

Memory device and in-memory computing method for binarized neural network

AssigneeMacronix International Co., Ltd.

InventorWen-Che Tsai

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Abstract

A memory device and an in-memory computing method are provided. The memory device is, for example, a 3D NAND flash memory and provides a storage media with high-performance and high-capacity. In the memory device, an input parser provides initial address information and initial layer activation data. A readout data sensor and comparator reads initial data corresponding to the initial address information from a memory array, and compares the initial layer activation data with a plurality of weight data in the initial data bit by bit respectively to generate a plurality of first comparative data. An error bit detector analyzes the first comparative data to generate a plurality of first analysis data. An operation circuit uses an activation function to operate each first analysis data and a corresponding second analysis data to provide intermediate layer activation data to the input parser.

Claims19

Dependent claims

A memory device, comprising:

an input parser, configured to receive an input data and providing initial address information and an initial layer activation data based on the input data;
a memory array, coupled to the input parser;
a readout data sensor and comparator, coupled to the input parser and the memory array, and configured to, in a case that the initial address information is provided by the input parser, read an initial data corresponding to the initial address information from the memory array, and compare the initial layer activation data with a plurality of weight data in the initial data bit by bit respectively to generate a plurality of first comparative data;
an error bit detector, coupled to the readout data sensor and comparator, and configured to analyze the plurality of first comparative data to generate a plurality of first analysis data;
and
an operation circuit, coupled to the error bit detector and the input parser, and configured to use an activation function to operate each of the plurality of first analysis data and a corresponding second analysis data to provide an intermediate layer activation data to the input parser.

3 more elements

An in-memory computing method, comprising:

receiving an input data, and providing initial address information and an initial layer activation data according to the input data;
in a case of providing the initial address information, reading an initial data corresponding to the initial address information from a memory array, and comparing the initial layer activation data with a plurality of weight data in the initial data bit by bit respectively to generate a plurality of first comparative data;
analyzing the plurality of first comparative data to generate a plurality of first analysis data;
and
utilizing an activation function to operate each of the plurality of first analysis data and a corresponding second analysis data to provide an intermediate layer activation data.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/930,951Filed 29 Oct 2024
Published: US 2026/0119314 A130 Apr 2026
Granted: 6 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 11/1016
Using codes or arrangements adapted for a specific type of error: error in accessing a memory location, i.e. addressing error
G06F 11/102
Using codes or arrangements adapted for a specific type of error: error in check bits
G06F 11/1068
In individual solid state devices: in sector programmable memories, e.g. flash disk
G06N 3/04
Neural networks: architecture, e.g. interconnection topology