Protection in asynchronous finite state machine

A method for operating an asynchronous finite state machine circuit, the method comprising:

• monitoring a state fault condition associated with the AFSM circuit, wherein the state fault condition corresponds to no state being asserted within the AFSM circuit or more than one state simultaneously being asserted within the AFSM circuit;
• monitoring an output fault condition associated with the AFSM circuit;
• and
• generating a pulsed reset signal in response to detecting the state fault condition for a duration greater than a predetermined threshold, detecting the output fault condition, or a combination thereof, and wherein the pulsed reset signal causes the AFSM circuit to be reset to a reset or idle condition, the pulsed reset signal being asserted for a predetermined duration,
• wherein the predetermined duration is equal to or greater than a state transition in the AFSM circuit, and
• wherein a first state and a second state are simultaneously active during the transition.

A system, comprising:

• an asynchronous finite state machine (AFSM) circuit comprising a plurality of states;
• and
• a protection circuit coupled to the AFSM circuit, the protection circuit comprising:
• a state decoder circuit configured to generate a first state error signal in response to detecting a state fault condition associated with the AFSM circuit, the state fault condition corresponding to more than one state being simultaneously asserted within the AFSM circuit,
• a fault de-glitch subcircuit configured to receive the first state error signal and generate a second state error signal in response to the first state error signal being asserted for a duration greater than a predetermined threshold, and
• a set/reset register configured to generate a pulsed reset signal in response to the second state error signal being generated by the fault de-glitch subcircuit, the pulsed reset signal being asserted for a predetermined duration,
• wherein the pulsed reset signal causes the AFSM circuit to be reset to a reset or idle condition.