Dataflow-based general-purpose processor architectures with feedforward register lanes
AssigneeThe Board of Trustees of the University of Illinois
InventorsNam Sung Kim, Dong Kai Wang
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Abstract
A dataflow-based general-purpose processor architecture and its method are disclosed. A circuit for the dataflow-based general-purpose processor architecture includes multiple processing elements (PEs) corresponding to multiple assigned central processing unit (CPU) instructions in program order, a register file, and multiple feedforward register lanes configured to map each of the multiple assigned CPU instructions on the multiple PEs to the register file or another PE of the multiple PEs to construct a hardware datapath corresponding to a dataflow graph of the multiple assigned CPU instructions. Other aspects, embodiments, and features are also claimed and described.
Claims21
A circuit for a dataflow-based general-purpose processor architecture comprising:
- a plurality of processing elements (PEs), each PE in the plurality of PEs comprising a source register and a destination register;
- a plurality of assigned central processing unit (CPU) instructions comprising a first instruction assigned to a first PE of the plurality of PEs;
- a register file separate from the PEs and comprising an array of a plurality of processor registers;
- and
- a plurality of feedforward register lanes that interconnect the PEs and the register file, and that are configured to map each of the plurality of assigned CPU instructions on the plurality of PEs to the register file or another PE of the plurality of PEs to construct a hardware datapath corresponding to a dataflow graph of the plurality of assigned CPU instructions,
- wherein the first instruction specifies a first register lane of the plurality of feedforward register lanes as a first source lane, a second register lane of the plurality of feedforward register lanes as a second source lane, and a third register lane of the plurality of feedforward register lanes as a destination lane, and
- wherein the first PE is configured to:
- read a first operand from the first register lane when a first valid bit corresponding to the first register lane indicates the first operand is valid;
- read a second operand from the second register lane when a second valid bit corresponding to the second register lane indicates the second operand is valid;
- execute the first instruction using the first and second operands;
- and
- output a result of the first instruction on the third register lane and set a third valid bit corresponding to the third register lane to indicate the result is valid.
A method for a dataflow-based general-purpose processor architecture, comprising:
- assigning a plurality of central processing unit (CPU) instructions to a plurality of processing elements (PEs) in program order, each of the plurality of PEs comprising a source register and a destination register;
- mapping a plurality of feedforward register lanes to the plurality of PEs corresponding to the plurality of CPU instructions to erect a hardware datapath corresponding to a dataflow graph of the plurality of assigned CPU instructions, wherein the plurality of feedforward register lanes interconnect the PEs and a register file that is separate from the PEs and comprises an array of a plurality of processor registers;
- concurrently executing at least two assigned CPU instructions of the plurality of assigned CPU instructions, wherein a first instruction of the at least two assigned CPU instructions is assigned to a first PE of the plurality of PEs and specifies a first register lane of the plurality of feedforward register lanes as a first source lane, a second register lane of the plurality of feedforward register lanes as a second source lane, and a third register lane of the plurality of feedforward register lanes as a destination lane;
- reading a first operand from the first register lane when a first valid bit corresponding to the first register lane indicates the first operand is valid;
- reading a second operand from the second register lane when a second valid bit corresponding to the second register lane indicates the second operand is valid;
- executing, by the first PE, the first instruction using the first and second operands;
- outputting, by the first PE, a result of the first instruction on the third register lane and setting a third valid bit corresponding to the third register lane to indicate the result is valid;
- and
- committing the plurality of CPU instructions in program order.
Dependencies are inferred from the claim text.