Quad-data-rate (QDR) host interface in a memory system
AssigneeRambus Inc.
InventorsLei Luo, John C Eble, III
Life of this patent
Estimating the term…
Abstract
Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described. One memory module includes a data buffer device with a host-side interface circuit that sends or receives first data to and from a host device at a quad data rate and a memory-side interface circuit that sends or receives second data to and from a set of memory devices at a first specified data rate that is less than the quad data rate. The memory module includes conversion circuitry to down-convert the first data at the quad data rate to the second data at the first specified data rate and up-convert the second data at the first specified data rate to the first data at the quad data rate.
Claims20
A memory module comprising:
- a plurality of memory devices organized as a plurality of memory channels, each memory device of the plurality of memory devices is to transfer data at a double data rate (DDR) such that two bits of data are transferred with respect to each clock cycle of a reference clock;
- a first set of data buffer devices, each data buffer device in the first set being coupled to memory devices in a first subset of the plurality of memory channels;
- a second set of data buffer devices, each data buffer device in the second set being coupled to memory devices in a second subset of the plurality of memory channels;
- and
- the first and second sets of data buffer devices having a host side interface to be coupled to a host device, wherein the first set of data buffer devices and the second set of data buffer devices are to transfer data at a quad data rate (QDR) on the host side interface, such that four bits of data are transferred with respect to each clock cycle of the reference clock.
A memory module comprising:
- a plurality of memory devices to send or receive data at a double data rate (DDR) for which two bits are transferred on a data line with respect to each clock cycle of a reference clock;
- one or more data buffer devices coupled to the plurality of memory devices, each of the one or more data buffer devices comprising:
- a first interface circuit to send or receive first data to and from a host device at a quad data rate (QDR) for which four bits are transferred on a data line with respect to each clock cycle of the reference clock;
- a second interface circuit to send or receive second data to and from the plurality of memory devices at the DDR;
- and
- first conversion circuitry to down-convert the first data at the QDR to the second data at the DDR and up-convert the second data at the DDR to the first data at the QDR;
- and
- a command buffer device coupled to the plurality of memory devices, the command buffer device comprising:
- a third interface circuit to receive first commands from the host device at the QDR;
- a fourth interface circuit to send second commands, corresponding to the first commands, to the plurality of memory devices at a first specified data rate;
- and
- second conversion circuitry to down-convert the first commands at the QDR to the second commands at the first specified data rate.
A method of operation of a memory module, the method comprising:
- receiving, by a data buffer device, first data from a plurality of memory devices at a double data rate (DDR) for which two bits are transferred on a data line with respect to each clock cycle of a reference clock;
- sending, by the data buffer device, the first data to a host device at a quad data rate (QDR) for which four bits are transferred on a data line with respect to each clock cycle of the reference clock;
- receiving, by the data buffer device, second data from the host device at the QDR;
- sending, by the data buffer device, the second data to the plurality of memory devices at the DDR;
- receiving, by a command buffer device, first commands from the host device at the QDR;
- sending, by the command buffer device, second commands, corresponding to the first commands, to the plurality of memory devices at a first specified data rate;
- and
- down-converting the first commands at the QDR to the second commands at the first specified data rate.
Dependencies are inferred from the claim text.