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US 12,754,674 B2Granted
Managing read timing in semiconductor devices
AssigneeMacronix International Co., Ltd.
InventorsWu-Chin Peng, Ken-Hui Chen, Chun-Hsiung Hung
Life of this patent
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Abstract
Systems, devices, methods, and circuits for managing read timing in semiconductor devices are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to read stored data from the memory array. The circuitry is configured to: obtain a starting address of target data to be read based on a read instruction, determine that the starting address is in a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective reading speed, and read out the target data from the memory array based on the starting address being in the first address group.
Claims20
A semiconductor device, comprising:
- a memory cell array comprising a plurality of memory cells configured to store data;
- and
- a circuitry coupled to the memory cell array and configured to read stored data from the memory cell array, wherein the circuitry comprises a timing profile controller and a sense amplifier,
- wherein the circuitry is configured to:
- obtain a starting address of target data to be read from the memory cell array based on a read instruction;
- determine that the starting address is in a first address group of a plurality of address groups, wherein each of the plurality of address groups is associated with a respective reading speed, and wherein the plurality of address groups correspond to one or more read regions of the memory cell array;
- configure, by the timing profile controller, a first timing profile for the first address group, the first timing profile being associated with a first reading speed for the first address group;
- and
- receive, by the sense amplifier, the first timing profile transmitted from the timing profile controller, and read out, by the sense amplifier, the target data from the memory cell array according to the first timing profile that is configured based on the starting address being in the first address group.
6 more elements
A system, comprising:
- a memory device;
- and
- a controller coupled to the memory device and configured to transmit a read instruction to the memory device,
- wherein the memory device comprises:
- a memory cell array comprising a plurality of memory cells configured to store data;
- and
- a circuitry coupled to the memory cell array and configured to read stored data from the memory cell array, wherein the circuitry comprises a timing profile controller and a sense amplifier,
- wherein the circuitry is configured to:
- obtain a starting address of target data to be read based on the read instruction;
- determine that the starting address is in a first address group of a plurality of address groups, wherein each of the plurality of address groups is associated with a respective reading speed, and wherein the plurality of address groups correspond to one or more read regions of the memory cell array;
- configure, by the timing profile controller, a first timing profile for the first address group, the first timing profile being associated with a first reading speed for the first address group;
- receive, by the sense amplifier, the first timing profile transmitted from the timing profile controller, and read out, by the sense amplifier, the target data from the memory cell array according to the first timing profile that is configured based on the starting address being in the first address group;
- and
- output the read out target data to the controller.
11 more elements
A method, comprising:
- obtaining a starting address of target data to be read from a memory cell array comprising a plurality of memory cells;
- determining that the starting address is in a first address group of a plurality of address groups, wherein each of the plurality of address groups is associated with a respective reading speed, and the first address group is associated with a first reading speed, and wherein the plurality of address groups correspond to one or more read regions of the memory cell array;
- configuring, by a timing profile controller, a first timing profile for the first address group, the first timing profile being associated with the first reading speed for the first address group;
- receiving, by a sense amplifier, the first timing profile transmitted from the timing profile controller;
- and
- reading out, by the sense amplifier, the target data from the memory cell array with the first reading speed according to the first timing profile that is configured based on the starting address being in the first address group.
3 more elements
Dependencies are inferred from the claim text.