US 12,754,598 B2 · Dynamic voltage and frequency scaling for memory in heterogeneous core architectures

Abstract

Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to optimizing memory frequency based on the bandwidth and latency needs of heterogeneous processing cores in a computer system. According to various embodiments, adjustments to the frequency of memory may be applied differently depending on the type of core requesting more bandwidth and/or faster response. According to various embodiments, the frequency is increased more sparingly for energy-efficient cores, while the frequency is increased more generously for high-performance cores. Additionally, when memory traffic decreases, the frequency of memory is decreased more generously when the previous request for higher frequency was from an energy-efficient core than a high-performance core. By considering the type of core that is requesting more bandwidth and/or faster response, performance and power consumption may be more optimally balanced.

Claims20

Dependent claims

An apparatus comprising:

a memory controller coupled to a first processing core and a second processing core, wherein the first processing core has a higher performance than the second processing core, the memory controller comprising:
a frequency optimizer configured to receive a memory bandwidth increase request and, based on the memory bandwidth increase request, to increase an operating frequency of a memory coupled to the memory controller, wherein the frequency optimizer is configured to increase the operating frequency of the memory in successive first increments based on the first processing core requesting the memory bandwidth increase request until the first processing core no longer requests a memory bandwidth increase, and to increase the operating frequency of the memory in successive second increments, smaller than the first increment, based on the second processing core requesting the memory bandwidth increase request until the second processing core no longer requests a memory bandwidth increase.

Dependencies are inferred from the claim text.

Dynamic voltage and frequency scaling for memory in heterogeneous core architectures

Life of this patent

Dynamic voltage and frequency scaling for memory in heterogeneous core architectures

Life of this patent

Abstract

Claims20