Low-dropout regulator and chip
AssigneeHuawei Technologies Co., Ltd.
InventorJinhai Zhang
Life of this patent
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Abstract
A low-dropout regulator includes a first power transistor, where the first power transistor is a first NMOS transistor, a drain of the first NMOS transistor is coupled to a power supply end, a source of the first NMOS transistor is configured to provide an output current for a load, and a gate of the first NMOS transistor is configured to receive a second feedback voltage; an error amplifier, where the error amplifier is a common-gate amplifier and is configured to generate a first feedback voltage based on an output voltage provided for the load and a reference voltage; and a loop gain amplifier, where the loop gain amplifier is a common-source amplifier and is configured to generate the second feedback voltage based on the first feedback voltage.
Claims20
A low-dropout regulator, comprising:
- an error amplifier configured to generate a first feedback voltage based on a reference voltage and an output voltage for a load, wherein the error amplifier is a common-gate amplifier;
- a power supply end;
- a first power transistor, wherein the first power transistor is a first N-channel metal-oxide-semiconductor (NMOS) transistor comprising:
- a first drain coupled to the power supply end;
- a first source configured to provide an output current for the load;
- and
- a first gate configured to receive a second feedback voltage;
- a loop gain amplifier configured to generate the second feedback voltage based on the first feedback voltage, wherein the loop gain amplifier is a common-source amplifier;
- a second power transistor, wherein the second power transistor is a second NMOS transistor comprising a second gate;
- and
- a low-pass filter separately coupled to the power supply end and the second gate.
A chip comprising:
- a supply voltage input end configured to provide a supply voltage;
- an analog circuit;
- and
- a low-dropout regulator configured to perform low-dropout regulation on the supply voltage to generate an output voltage for a load, configured to supply power to the analog circuit based on the output voltage, and comprising:
- an error amplifier configured to generate a first feedback voltage based on a reference voltage and the output voltage, wherein the error amplifier is a common-gate amplifier;
- a power supply end;
- a first power transistor, wherein the first power transistor is a first N-channel metal-oxide semiconductor (NMOS) transistor comprising:
- a first drain coupled to the power supply end;
- a first source configured to provide an output current for the load;
- and
- a first gate configured to receive a second feedback voltage;
- a loop gain amplifier configured to generate the second feedback voltage based on the first feedback voltage, wherein the loop gain amplifier is a common-source amplifier;
- a second power transistor, wherein the second power transistor is a second NMOS transistor comprising a second gate;
- and
- a low-pass filter separately coupled to the power supply end and the second gate.
Dependencies are inferred from the claim text.