Receiver of an UWB radar device and operating method thereof

A method of operating a receiver of a radar device, comprising:

• receiving, by the receiver of the radar device, a reflected pulse signal having a first period from an outside;
• sampling, by a sampling circuit, the reflected pulse signal as a first received signal in response to a clock signal having a second period equal to the first period;
• generating, by an integration circuit, an analog integration signal based on the first received signal and a control signal, in response to the clock signal;
• comparing, by a comparison circuit, a magnitude of the analog integration signal with a magnitude of a reference signal, in response to the clock signal;
• adjusting, by the comparison circuit, a count value and the control signal based on a result of comparing the magnitude of the analog integration signal with the magnitude of the reference signal;
• and
• converting, by an ADC circuit, the analog integration signal into a digital integration signal.

A radar device comprising:

• a receiver configured to receive a reflected pulse signal having a first period reflected from a detection target;
• and
• a processor configured to control the receiver and to receive data associated with the detection target from the receiver,
• wherein the receiver includes:
• a sampling circuit configured to sample the reflected pulse signal as a first received signal in response to a clock signal having a second period equal to the first period;
• an integration circuit configured to, in response to the clock signal, generate an analog integration signal based on the first received signal and a control signal;
• a comparison circuit configured to, in response to the clock signal, adjust a count value and the control signal based on a result of comparing the analog integration signal with a reference signal, output the control signal to the integration circuit, and output the count value to the processor;
• and
• an ADC circuit configured to convert the analog integration signal into a digital integration signal, and to output the digital integration signal to the processor,
• wherein the count value is implemented as an M-bit digital signal, and the analog integration signal is implemented as an L-bit digital signal,
• wherein each of the “M” and the “L” is an arbitrary integer greater than or equal to “0”, and
• wherein the processor is configured to place the count value in an MSB and to place the analog integration signal in a LSB to obtain a voltage corresponding to the reflected pulse signal.