Chip-on-wafer-on-board structure using spacer die and methods of forming the same

A semiconductor structure comprising:

• an interposer comprising:
• a lower interposer including a redistribution structure;
• and
• an upper interposer on the lower interposer and including a plurality of bump structures;
• a semiconductor die attached to the interposer by the plurality of bump structures, wherein the semiconductor die comprises a plurality of semiconductor dies and the upper interposer comprises a local silicon interconnect (LSI) die configured to interconnect the plurality of semiconductor dies;
• a spacer structure attached to the interposer by the plurality of bump structures and laterally adjacent the semiconductor die;
• and
• a molding material layer on the interposer around the semiconductor die and the spacer structure.

A semiconductor structure comprising:

• an interposer including a redistribution structure;
• a plurality of semiconductor dies attached to the interposer by a plurality of bump structures, wherein the plurality of semiconductor dies comprises a functional die and a high bandwidth memory (HBM) die adjacent the functional die;
• a spacer structure attached to the interposer by the plurality of bump structures and laterally surrounding the plurality of semiconductor dies, wherein an upper surface of the spacer structure is aligned with an upper surface of the plurality of semiconductor dies;
• a molding material layer on the interposer around the plurality of semiconductor dies and the spacer structure, wherein a sidewall of the molding material layer is aligned with a sidewall of the interposer;
• a printed circuit board, wherein the redistribution structure of the interposer is attached to the printed circuit board;
• and
• a ball grid array on a bottom surface of the redistribution structure, wherein the redistribution structure is attached directly to the printed circuit board by the ball grid array.