Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package, comprising:

• a package substrate having a first opening in a chip mounting region and a plurality of first substrate pads in the chip mounting region, the package substrate having a plurality of second substrate pads in a region surrounding the chip mounting region;
• a first semiconductor chip mounted on the chip mounting region and having a plurality of first chip pads;
• a plurality of first conductive connection members electrically connecting the plurality of first chip pads to the plurality of the first substrate pads, respectively;
• a plurality of second semiconductor chips stacked on an upper surface of the package substrate and having a front surface and a backside surface facing each other, each of the plurality of second semiconductor chips having a plurality of second chip pads disposed on the front surface;
• a plurality of adhesive films, each of the plurality of adhesive films attached to the backside surface of each of the plurality of second semiconductor chips;
• a plurality of second conductive connection members electrically connecting the plurality of second chip pads to the plurality of the second substrate pads, respectively;
• and
• a sealant covering the first semiconductor chip, the plurality of second semiconductor chips and the second conductive connection members on the package substrate, the sealant filling a gap between the first semiconductor chip and the package substrate and filling an interior of the first opening of the package substrate.

A semiconductor package, comprising:

• a package substrate having a first opening in a chip mounting region and a plurality of first substrate pads in the chip mounting region, the package substrate having a plurality of second substrate pads in a region excluding the chip mounting region;
• a first semiconductor chip mounted on the chip mounting region and a plurality of first chip pads on the first semiconductor chip;
• a plurality of first conductive connection members electrically connecting the plurality of first chip pads to the plurality of the first substrate pads, respectively;
• a plurality of second semiconductor chips stacked on an upper surface of the package substrate and having a front surface and a backside surface facing each other, each of the plurality of second semiconductor chips having a plurality of second chip pads disposed on the front surface;
• a plurality of adhesive films, each of the plurality of adhesive films attached to the backside surface of each of the plurality of the plurality of second semiconductor chips;
• a plurality of second conductive connection members electrically connecting the plurality of second chip pads to the plurality of the second substrate pads, respectively;
• a sealant covering the first semiconductor chip, the plurality of second semiconductor chips and the second conductive connection members on the package substrate, the sealant filling a gap between the first semiconductor chip and the package substrate and filling an interior of the first opening of the package substrate;
• and
• a taping film attached on a lower surface of the package substrate such that at least a portion of the sealant exposed in the first opening is covered,
• wherein a lower surface of a portion of the sealant filling the interior of the first opening is coplanar with the lower surface of the package substrate,
• wherein a width of the first opening in a first direction is smaller than a width of the first opening in a second direction perpendicular to the first direction,
• wherein the width of the first opening in the second direction is less than or equal to a length of the first semiconductor chip in the second direction.