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US 12,751,291 B2Granted
Semiconductor structures including auxetic microstructures and method of forming the same
AssigneeSanDisk Technologies LLC
InventorYushi Yokomizo
Life of this patent
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Abstract
A semiconductor structure includes a semiconductor device substrate, and an auxetic microstructure containing an auxetic matrix having a negative Poission's ratio.
Claims11
A semiconductor structure, comprising:
- a semiconductor device substrate comprising a semiconductor material having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm;
- and
- an auxetic microstructure located in or over the semiconductor device substrate and comprising an auxetic matrix having a negative Poisson's ratio;
- wherein:
- the semiconductor device substrate comprises a semiconductor substrate containing the semiconductor material and the auxetic matrix, and the auxetic matrix comprises a portion of the semiconductor material;
- the auxetic matrix comprises a protruding portion of the semiconductor material in the semiconductor substrate;
- and
- the plurality of fill material portions comprise dielectric material portions located in the openings within the protruding portion of the semiconductor material in the semiconductor substrate.
5 more elements
A semiconductor structure, comprising:
- a semiconductor device substrate comprising a semiconductor material having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm;
- an auxetic microstructure located in or over the semiconductor device substrate and comprising an auxetic matrix having a negative Poisson's ratio;
- and
- semiconductor devices located over a top side of the semiconductor device substrate, wherein the auxetic matrix comprises a portion of the semiconductor material and is located in a bottom side of the semiconductor device substrate which is opposite to the top side of the semiconductor device substrate.
1 more element
A semiconductor structure, comprising:
- a semiconductor device substrate comprising a semiconductor material having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm;
- an auxetic microstructure located in or over the semiconductor device substrate and comprising an auxetic matrix having a negative Poisson's ratio;
- and
- a three-dimensional memory array located on the semiconductor device substrate and comprising:
- an alternating stack of insulating layers and electrically conductive layers;
- memory openings vertically extending through the alternating stack;
- and
- memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements, wherein the auxetic matrix is embedded within the three-dimensional memory array.
5 more elements
Dependencies are inferred from the claim text.