Semiconductor package and semiconductor package assembly with edge interconnection and method of forming the same

An IC stack comprising:

• a plurality of integrated circuit (IC) structure horizontally separate with each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall;
• wherein an area of the bottom surface or the top surface is larger than that of any of the four sidewalls, and each IC structure comprises:
• a first semiconductor body having a first primary surface and a first secondary surface, and the first semiconductor body includes a first edge connection aligned with the first secondary surface;
• and
• an interconnection structure including a primary redistribution layer (RDL) over the first primary surface;
• wherein the primary RDL includes a second edge connection aligned with the first secondary surface of the first semiconductor body;
• and
• a laterally extending RDL structure covering each first sidewall of the plurality of IC structures, the laterally extending RDL structure further electrically connected to the first edge connection and/or the second edge connection.

An IC stack comprising:

• a plurality of integrated circuit (IC) structures horizontally separated with each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall;
• wherein an area of the bottom surface or the top surface is larger than that of any sidewall;
• a laterally extending RDL structure covering each first sidewall of the plurality of IC structures, wherein the laterally extending RDL structure comprises:
• a front interconnect surface with a set of front contacting pads coupled with the first sidewall of each IC structure;
• and
• a back interconnect surface opposite to the front interconnect surface, wherein the back interconnect surface includes a set of back contacting pads;
• an upward extending thermal conductivity layer between two adjacent IC structures;
• and
• a logic control chip under and electrically connected to the laterally extending RDL structure of the IC stack,
• wherein each of the IC structures comprises a DRAM semiconductor die comprising a plurality of memory I/O pads, the logic control chip comprises a plurality of logic I/O pads, and the plurality of memory I/O pads of each DRAM semiconductor die are electrically coupled to the plurality of logic I/O pads through the laterally extending RDL structure, and wherein the plurality of IC structures are electrically coupled to the logic control chip through the set of back contacting pads of the back interconnect surface of the laterally extending RDL structure.