Semiconductor package with a carbonized modified layer covered by a passivation layer

A semiconductor package comprising:

• a substrate including an active surface and an inactive surface;
• a plurality of wiring structures arranged on the active surface of the substrate;
• an inter-wiring insulating layer arranged on the active surface of the substrate and covering the plurality of wiring structures, the inter-wiring insulating layer comprising a main region and an edge region surrounding the main region in a plan view;
• a modified layer arranged between the main region and the edge region of the inter-wiring insulating layer and comprising a carbonized form of a material constituting the inter-wiring insulating layer;
• and
• a passivation layer arranged on the inter-wiring insulating layer and the modified layer, wherein the passivation layer comprises a first portion on the modified layer and a second portion on the main region of the inter-wiring insulating layer, and a bottom surface of the first portion of the passivation layer is at a same level as a bottom surface of the second portion of the passivation layer.

A semiconductor package comprising:

• a buffer die including a first semiconductor substrate, the first semiconductor substrate comprising:
• a first active surface and a first inactive surface, wherein the first active surface is opposite to the first inactive surface;
• and
• a plurality of first through electrodes penetrating the first semiconductor substrate, wherein a first inter-wiring insulating layer is on the first active surface of the first semiconductor substrate, a first front surface insulating layer is on the first inter-wiring insulating layer, and a first rear surface insulating layer is on the first inactive surface of the first semiconductor substrate;
• a plurality of memory dies stacked on the buffer die, each memory die including a second semiconductor substrate, the second semiconductor substrate comprising:
• a second active surface and a second inactive surface, wherein the second active surface is opposite to the second inactive surface;
• and
• a plurality of second through electrodes penetrating the second semiconductor substrate, wherein a second inter-wiring insulating layer is on the second active surface, wherein a second front surface insulating layer is on the second inter-wiring insulating layer, wherein a second rear surface insulating layer is on the second inactive surface, and wherein the second active surface of each memory die is arranged toward the first inactive surface of the buffer die;
• a plurality of first bonding pads arranged between a lowermost memory die of the plurality of memory dies and the buffer die, and surrounded by the second front surface insulating layer of the lowermost memory die and the first rear surface insulating layer;
• and
• a plurality of second bonding pads arranged between two adjacent memory dies of the plurality of memory dies, and surrounded by the second front surface insulating layer and the second rear surface insulating layer arranged between two adjacent memory dies of the plurality of memory dies, wherein the first inter-wiring insulating layer comprises a first region arranged on a chip region of the buffer die and a second region arranged on a scribe lane region of the buffer die, and the first region is apart from the second region by a modified layer arranged between the first region and the second region.