Semiconductor storage device and manufacturing method thereof

A semiconductor storage device comprising:

• a first layer including a first surface and a second surface located opposite to the first surface, the first layer including a first memory cell array and a first wire layer, the first memory cell array being provided between the first surface and the second surface and including a plurality of first memory cells, and the first wire layer facing the first surface and being electrically connected to the first memory cells;
• a second layer including a third surface and a fourth surface located opposite to the third surface, the second layer including a second memory cell array provided between the third surface and the fourth surface to be electrically connected to the first wire layer and including a plurality of second memory cells, the second layer further including a first pad facing the third surface and electrically connected to the second memory cells;
• a third layer including a fifth surface and a sixth surface located opposite to the fifth surface, the third layer including a CMOS circuit provided between the fifth surface and the sixth surface to be electrically connected to the first and second memory cells and the first wire layer;
• a fourth layer including a seventh surface and an eighth surface located opposite to the seventh surface, the fourth layer including a third wire layer to be electrically connected to the first and second memory cells, the first wire layer and the CMOS circuit;
• a contact plug penetrating the fourth layer and the second layer and electrically connected to the first wire layer;
• and
• a second pad electrically connected to the contact plug on the seventh surface, wherein
• the first layer and the second layer are joined together on the first surface and the third surface,
• the first layer and the third layer are joined together on the second surface and the fifth surface,
• the second layer and the fourth layer are joined together via the fourth surface and the eighth surface,
• the first wire layer and the first pad are directly joined together via the first surface and the third surface, and
• the first wire layer is set to a predetermined source voltage through the second pad and the contact plug.