Semiconductor chip with stepped sidewall, semiconductor package including the same, and method of fabricating the same

A semiconductor chip, comprising:

• a substrate including a device region and an edge region;
• a device layer and a wiring layer sequentially stacked on the substrate;
• a residual test pattern and a sub-pad on the wiring layer, the sub-pad being on the device region, the residual test pattern being on the edge region, and a sidewall of the residual test pattern being aligned with a sidewall of the substrate;
• an upper dielectric stack covering the sub-pad and the residual test pattern;
• a passivation layer on the upper dielectric stack;
• a separation dielectric pattern penetrating the wiring layer on the edge region;
• a bonding pad in the upper dielectric stack and connected to the sub-pad;
• a conductive bump penetrating the passivation layer and coupled to the bonding pad;
• and
• a solder layer coupled to the conductive bump,
• wherein the upper dielectric stack exposes a portion of a top surface of the residual test pattern,
• wherein a sidewall of the upper dielectric stack has a stepped region,
• wherein a top surface of the bonding pad is at a first depth from a top surface of the passivation layer,
• wherein a bottom surface of the stepped region is at a second depth from the top surface of the passivation layer, and
• wherein the second depth is about 0.9 times to about 2.0 times the first depth.

A semiconductor chip, comprising:

• a substrate including a device region and an edge region;
• a device layer and a wiring layer sequentially stacked on the substrate;
• a residual test pattern and a sub-pad on the wiring layer, the sub-pad being on the device region, the residual test pattern being on the edge region, and a sidewall of the residual test pattern being aligned with a sidewall of the substrate;
• and
• an upper dielectric stack that covers the sub-pad and the residual test pattern,
• wherein the upper dielectric stack exposes a portion of a top surface of the residual test pattern,
• wherein the device layer includes a device interlayer dielectric layer,
• wherein the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
• wherein a surface roughness at a sidewall of an uppermost one of the upper dielectric layers is less than a surface roughness at a sidewall of the device interlayer dielectric layer.