Back to results
US 12,751,271 B2Granted
Gate all around backside power rail with diffusion break
AssigneeApplied Materials, Inc.
InventorsAndrew Yeoh, Benjamin Colombeau, Balasubramanian Pranatharthiharan, El Mehdi Bazizi, Ashish Pal
Life of this patent
Estimating the term…
Abstract
Semiconductor devices and methods of manufacturing the same are described. The method includes forming a diffusion break opening on the backside and filling with a diffusion break material to serve as a planarization stop. In some embodiments, a single diffusion break opening is formed. In other embodiments, a mixed diffusion break opening is formed.
Claims18
A method of forming a semiconductor device, the method comprising:
- forming a gate structure on a superlattice structure, the superlattice structure on a top surface of a shallow trench isolation on a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs;
- forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate;
- depositing a bottom dielectric isolation layer in the plurality of source trenches and the plurality of drain trenches;
- forming a resist on a top surface of the gate structure;
- patterning the resist to expose the superlattice structure and the bottom dielectric isolation layer, and form a diffusion break opening, the diffusion break opening extending from the top surface of the gate structure to the shallow trench isolation;
- depositing a diffusion break material in the diffusion break opening, the diffusion break material comprising both a dielectric material and a metal;
- planarizing the semiconductor device;
- etching to form a plurality of via openings extending to the bottom dielectric isolation layer;
- and
- depositing a metal in the plurality of via openings to form a plurality of vias.
7 more elements
A method of forming a semiconductor device, the method comprising:
- forming a plurality of source trenches and a plurality of drain trenches adjacent to a superlattice structure on a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs;
- expanding at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity;
- depositing a bottom isolation dielectric layer in the source cavity and in the drain cavity;
- forming a resist on a gate structure, the gate structure adjacent the superlattice structure on the substrate;
- patterning the resist to form at least one diffusion break opening;
- depositing a diffusion break material in the at least one diffusion break opening, the diffusion break material comprising both a dielectric material and a metal;
- rotating the semiconductor device 180 degrees;
- planarizing the semiconductor device;
- forming a backside power rail via in the substrate to the bottom dielectric isolation layer;
- and
- depositing a metal in the backside power rail via.
8 more elements
Dependencies are inferred from the claim text.