Technologies for aligned vias
AssigneeIntel Corporation
InventorsChanghua Liu, Leonel R. Arana, Jeremy D. Ecton, Suddhasattwa Nad, Brandon Christian Marin
Life of this patent
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Abstract
Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity and low-photosensitivity photoresist are applied to a substrate and exposed at the same time with use of a dual-tone mask. After being developed, one photoresist forms an overhang over a sheltered region. The mold formed by the photoresists is filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the sheltered region forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.
Claims25
A method comprising:
- applying a first layer comprising a photoresist having a first photosensitivity to a substrate;
- applying a second layer comprising a photoresist having a second photosensitivity to the first layer comprising a photoresist, wherein the second photosensitivity is different from the first photosensitivity;
- exposing the first layer and the second layer with electromagnetic radiation with use of a multi-tone photomask, wherein the electromagnetic radiation through one or more gray regions of the multi-tone photomask exposes one and not the other of the first layer and the second layer;
- developing the first layer and the second layer, wherein the developed first layer defines a mold, wherein the mold comprises a conductive trace region and a via region, wherein the developed second layer comprises an overhang region that extends over the via region;
- filling the mold defined by the first layer with a conductive infill;
- and
- applying an etchant to the conductive infill, wherein the etchant etches the conductive infill from a top surface of the conductive infill to create a conductive trace in the conductive trace region, wherein the etchant laterally etches the conductive infill under the overhang region to create a via in the via region.
A method comprising:
- applying a first layer comprising a photoresist to a substrate;
- exposing the first layer;
- developing the first layer, wherein the developed first layer defines a mold;
- filling the mold defined by the first layer with a conductive infill;
- applying a second layer comprising a photoresist to the developed first layer and the conductive infill;
- exposing the second layer;
- developing the second layer, wherein the developed second layer does not extend over a conductive trace region of the mold, wherein the developed second layer comprises an overhang region that extends over a via region of the mold defined by the first layer;
- and
- applying an etchant to the conductive infill, wherein the etchant etches the conductive infill from a top surface of the conductive infill to create a conductive trace in the conductive trace region, wherein the etchant laterally etches the conductive infill under the overhang region to create a via in the via region.
A method comprising:
- a step for applying a first layer comprising a photoresist and a second layer comprising a photoresist to a substrate, wherein the second layer has an overhang region that extends over a region of the substrate not covered by the first layer;
- a step for filling a mold defined by the first layer with a conductive infill;
- and
- a step for etching the conductive infill to create a conductive trace by removing part of the conductive infill adjacent to the conductive trace and a via by removing part of the conductive infill adjacent to the via.
A method for fabricating an electronic component comprising:
- applying photoresist layers to a substrate;
- exposing and developing the photoresist layers to form a mold defining multiple conductive regions and multiple via regions;
- filling the mold with a conductive material;
- etching the conductive material while using an overhang structure to protect portions of the conductive material in the via regions, thereby forming multiple conductive traces and multiple vias that are aligned to the conductive traces;
- and
- arranging the multiple conductive traces and multiple vias to form an electronic component selected from the group consisting of a capacitor, an inductor, a resistor, and a transmission line.
Dependencies are inferred from the claim text.