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US 12,751,214 B2Granted
Superconducting silicon transistor and fabrication thereof
AssigneeInternational Business Machines Corporation
InventorsMatthias Mergenthaler, Fabrizio Nichele, Markus Fabian Ritter
Life of this patent
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Abstract
A superconductor device includes a substrate. There is a first silicide and a second silicide located on opposite sides of a silicon channel and on top of the substrate. A first superconducting contact is in contact with the first silicide. A second superconducting contact is in contact with the second silicide. A dielectric is located between the first and second superconducting contacts. A gate is on top of the gate dielectric.
Claims20
A superconductor device, comprising:
- a substrate that comprises undoped silicon;
- a first silicide region comprising a first silicide and a second silicide region comprising a second silicide located on opposite sides of a silicon channel and on top of the substrate, wherein the first silicide and the second silicide are in direct contact with the undoped silicon;
- a first superconducting contact in contact with the first silicide region;
- a second superconducting contact in contact with the second silicide region;
- a gate dielectric located between the first superconducting contact and the second superconducting contact and in contact with the first silicide region, the second silicide region, and the substrate, wherein the gate dielectric entirely fills a gap between a first sidewall of the first superconducting contact and a second sidewall of the second superconducting contact, wherein the gap extends from the first sidewall of the first superconducting contact to the second sidewall of the second superconducting contact;
- and
- a gate in contact with the gate dielectric.
4 more elements
A quantum transistor device, comprising:
- a substrate that comprises undoped silicon;
- a first silicide region comprising a first silicide and a second silicide region comprising a second silicide located on opposite sides of a silicon channel and on top of the substrate, wherein the first silicide and the second silicide are in direct contact with the undoped silicon;
- a first superconducting contact in contact with the first silicide region;
- a second superconducting contact in contact with the second silicide region;
- a dielectric located between the first superconducting contact and the second superconducting contact and in contact with the first silicide region, the second silicide region, and the substrate, wherein the dielectric entirely fills a gap between a first sidewall of the first superconducting contact and a second sidewall of the second superconducting contact, wherein the gap extends from the first sidewall of the first superconducting contact to the second sidewall of the second superconducting contact;
- and
- a gate in contact with the dielectric.
4 more elements
A quantum chip, comprising:
- a substrate that comprises undoped silicon;
- a first silicide region comprising a first silicide and a second silicide region comprising a second silicide located on opposite sides of a silicon channel and on top of the substrate, wherein the first silicide and the second silicide are in direct contact with the undoped silicon;
- a first superconducting contact in contact with the first silicide region;
- a second superconducting contact in contact with the second silicide region;
- a dielectric located between the first superconducting contact and the second superconducting contact and in contact with the first silicide region, the second silicide region, and the substrate, wherein the dielectric entirely fills a gap between a first sidewall of the first superconducting contact and a second sidewall of the second superconducting contact, wherein the gap extends from the first sidewall of the first superconducting contact to the second sidewall of the second superconducting contact;
- and
- a gate in contact with the dielectric.
4 more elements
Dependencies are inferred from the claim text.